US4783749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Basic cell realized in the CMOS technique and a method for the automatic generation of such a basic cell
Assignee: Siemens AG
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Filing: 1986-04-15
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Granted: 1988-11-08
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Expires: 2006-04-15
Abstract
Abstract A basic cell constructed in accordance with the CMOS technique for building electronic circuits is provided, wherein a plurality of transistors, maximally four transistors, are arranged next to one another. First interconnects essentially composed of polysilicon are arranged parallel to the extent of the first transistors and second interconnects essentially composed of metal are arranged perpendicular to the first interconnects. The second interconnects extend either over the transistors or between the transistors. Transistors respectively arranged in one of two groups are combined to form a parallel or series circuit. Metal tracks are arranged in the basic cell outside of the transistor surfaces at the lateral cell edge. Polysilicon interconnects and/or metal interconnects are established perpendicular to the appertaining directions, namely parallel to the extent of the transistors or, respectively, perpendicular thereto. The interconnects are arranged such that a respective following interconnect has its course adapted to the contour of the previously defined interconnects. Further, required contacts at the interconnects are arranged shifted with respect to the interconnects connected thereto such that they are dislocated into a bay contained at the appertaining, neighboring interconnect.
Inventors
- 👤 Peter Duzy
- 👤 Ralf De Marino
- 👤 Berghardt Schallenberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/909; H10D84/935; H10D84/937; H10D84/938
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
In a basic cell of the type constructed in accordance with complementary-metal-oxide-semiconductor technology, in which a plurality of transistors are arranged next to one another, a plurality of polysilicon first interconnects are arranged parallel to the extent of the transistors, and a plurality of metal second interconnects are arranged perpendicular to the first interconnects and extend adjacent the transistors, the improvement wherein: a maximum of four transistors are provided per basic cell and comprising first and second groups, said transistors of said first group being n-channel transistors and the transistors of said second group being p-channel transistors, said first group located in a first region of the cell and said second group located in a second region of the cell; the transistors of said first group being interconnected to form a first circuit and the transistors of the second group being interconnected to form a second circuit; metal tracks are arranged in the cell outside of the transistor areas at a lateral cell edge; interconnects are provided adjacent said transistors and arranged such that an interconnect next following a previously formed interconnect extends adapted to the contour of the previously formed interconnect; and contacts are provided and arranged shifted with respect to interconnects connected thereto such that they are located in a bay formed in the appertaining neighboring interconnect.
Claim 2
Dependent Claim
219 words
In a basic cell of the type constructed in accordance with complementary-metal-oxide-semiconductor technology, in which a plurality of transistors are arranged next to one another, a plurality of polysilicon first interconnects are arranged parallel to the extent of the transistors, and a plurality of metal second interconnects are arranged perpendicular to the first interconnects and extend adjacent the transistors, the improvement wherein: a maximum of four transistors are provided per basic cell and comprising first and second groups, said transistors of said first group being n-channel transistors and the transistors of said second group being p-channel transistors, said first group located in a first region of the cell and said second group located in a second region of the cell; the transistors of said first group being interconnected to form a first circuit and the transistors of the second group being interconnected to form a second circuit; metal tracks are arranged in the cell outside of the transistor areas at a lateral cell edge; interconnects are provided adjacent said transistors and arranged such that an interconnect next following a previously formed interconnect extends adapted to the contour of the previously formed interconnect; and contacts are provided and arranged shifted with respect to interconnects connected thereto such that they are located in a bay formed in the appertaining neighboring interconnect.
Claim 3
Dependent Claim
17 words
The improved basic cell of claim 1, wherein: the transistors of a group are connected in parallel.
Claim 4
Dependent Claim
17 words
The improved basic cell of claim 1, wherein: the transistors of a group are connected in series.
Claim 5
Dependent Claim
13 words
The improved basic cell of claim 1, wherein: the interconnects comprise different widths.
Claim 6
Independent Claim
264 words
A method of generating a basic cell of the type constructed in accordance with complementary-metal-oxide semiconductor technology, in which a plurality of transistors are arranged next to one another, a plurality of polysilicon first interconnects are arranged parallel to the extent of the transistors, and a plurality of metal second interconnects are arranged perpendicular to the first interconnects and extend adjacent the transistors, a maximum of four transistors are provided per basic cell and comprising first and second groups, said transistors of said first group being n-channel transistors and the transistors of said second group being p-channel transistors, said first group located in a first region of the cell and said second group located in a second region of the cell; the transistors of said first group being interconnected to form a first circuit and the transistors of the second group being interconnected to form a second circuit; metal tracks are arranged in the cell outside of the transistor areas at a lateral cell edge; interconnects are provided adjacent said transistors and arranged such that an interconnect next following a previously formed interconnect extends adapted to the contour of the previously formed interconnect; and contacts are provided and arranged shifted with respect to interconnects connected thereto such that they are located in a bay formed in the appertaining neighboring interconnect; comprising the steps of: describing the basic cell with a plurality of parameters; topologically optimizing the relative positions of the connection elements within the basic cell; and geometrically optimizing the arrangements of the individual elements of the basic cell to achieve optimum surface exploitation.
Claim 7
Independent Claim
264 words
A method of generating a basic cell of the type constructed in accordance with complementary-metal-oxide semiconductor technology, in which a plurality of transistors are arranged next to one another, a plurality of polysilicon first interconnects are arranged parallel to the extent of the transistors, and a plurality of metal second interconnects are arranged perpendicular to the first interconnects and extend adjacent the transistors, a maximum of four transistors are provided per basic cell and comprising first and second groups, said transistors of said first group being n-channel transistors and the transistors of said second group being p-channel transistors, said first group located in a first region of the cell and said second group located in a second region of the cell; the transistors of said first group being interconnected to form a first circuit and the transistors of the second group being interconnected to form a second circuit; metal tracks are arranged in the cell outside of the transistor areas at a lateral cell edge; interconnects are provided adjacent said transistors and arranged such that an interconnect next following a previously formed interconnect extends adapted to the contour of the previously formed interconnect; and contacts are provided and arranged shifted with respect to interconnects connected thereto such that they are located in a bay formed in the appertaining neighboring interconnect; comprising the steps of: describing the basic cell with a plurality of parameters; topologically optimizing the relative positions of the connection elements within the basic cell; and geometrically optimizing the arrangements of the individual elements of the basic cell to achieve optimum surface exploitation.
Claim 8
Dependent Claim
16 words
The method of claim 5, and further defined as: programming the method in the Pascal language.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |