Continuously variable slope delta modulation using digital vector for slope control

Claim 1

An apparatus responsive to a clock signal having serial clock cycles for digital encoding of a first analog signal, comprising: comparator means for comparing the first analog signal to a reconstructed analog signal and generating, during clock cycles, digital outputs having a first value when the analog signal is greater than the reconstructed first analog signal and a second value when the first analog signal is less than the reconstructed analog signal; integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, in serial clock cycles, for generating a m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), wher C j is true when B 1 through B m+j are equivalent, and n-2 is greater than or equal to m, and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector; means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector signal and said m-dimensional weighting vector during the given clock cycle, and filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal.

Claim 2

An apparatus responsive to a clock signal having serial clock cycles for digital encoding of a first analog signal, comprising: comparator means for comparing the first analog signal to a reconstructed analog signal and generating, during clock cycles, digital outputs having a first value when the analog signal is greater than the reconstructed first analog signal and a second value when the first analog signal is less than the reconstructed analog signal; integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, in serial clock cycles, for generating a m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), wher C j is true when B 1 through B m+j are equivalent, and n-2 is greater than or equal to m, and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector; means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector signal and said m-dimensional weighting vector during the given clock cycle, and filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal.

Claim 4

An apparatus responsive to a clock signal having serial clock cycles for digital encoding of a first analog signal, comprising: comparator means for comparing the first analog signal to a reconstructed analog signal and generating, during clock cycles, digital outputs having a first value when the first analog signal is greater than the reconstructed analog signal and a second value when the first analog signal is less than the reconstructed analog signal; integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, in serial clock cycles, for generating a m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal, is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent, and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector; means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector signal and said m-dimensional weighting vector during the given clock cycle, and filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal, wherein n is equal to 6 and m is equal to 3, and the digital outputs for the n serial clock cycles are defined as B 1 , B 2 , B 3 , B 4 , B 5 and B 6 ; and said m-dimensional vector is defined as C 1 , C 2 , and C 3 , where C 1 is true when B 1 through B 4 are equivalent, C 2 is true when B 1 through B 5 are equivalent and C 3 is true when B 1 through B 6 are equivalent; and said means for storing an m-dimensional weighting vector stores a vector defined as W 1 , W 2 , and W 3 , where W 1 is equal to k, W 2 is equal to 2k, and W 3 is equal to 4k, where k is a preselected parameter; and said scalar product signal indicates the sum of C 1 W 1 +C 2 W 2 +C 3 W 3 during the given clock cycle.

Claim 5

An apparatus responsive to a clock signal having serial clock cycles for digital encoding of a first analog signal, comprising: comparator means for comparing the first analog signal to a reconstructed analog signal and generating, during clock cycles, digital outputs having a first value when the first analog signal is greater than the reconstructed analog signal and a second value when the first analog signal is less than the reconstructed analog signal; integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, in serial clock cycles, for generating a m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal, is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent, and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector; means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector signal and said m-dimensional weighting vector during the given clock cycle, and filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal, wherein n is equal to 6 and m is equal to 3, and the digital outputs for the n serial clock cycles are defined as B 1 , B 2 , B 3 , B 4 , B 5 and B 6 ; and said m-dimensional vector is defined as C 1 , C 2 , and C 3 , where C 1 is true when B 1 through B 4 are equivalent, C 2 is true when B 1 through B 5 are equivalent and C 3 is true when B 1 through B 6 are equivalent; and said means for storing an m-dimensional weighting vector stores a vector defined as W 1 , W 2 , and W 3 , where W 1 is equal to k, W 2 is equal to 2k, and W 3 is equal to 4k, where k is a preselected parameter; and said scalar product signal indicates the sum of C 1 W 1 +C 2 W 2 +C 3 W 3 during the given clock cycle.

Claim 6

An apparatus responsive to a clock signal having serial clock cycles for reconstructing a first analog signal in response to digital signals including a plurality of digital outputs in serial clock cycles indicating a digital encoding of the first analog signal, comprising: integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, from n serial clock cycles, for generating an m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent, and n-2 is greater than or equal to m; and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector, means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector and said m-dimensional weighting vector during the given clock cycle, and means, responsive to the scalar product signal, for generating the slope control signal, including filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal.

Claim 7

An apparatus responsive to a clock signal having serial clock cycles for reconstructing a first analog signal in response to digital signals including a plurality of digital outputs in serial clock cycles indicating a digital encoding of the first analog signal, comprising: integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, from n serial clock cycles, for generating an m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent, and n-2 is greater than or equal to m; and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector, means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector and said m-dimensional weighting vector during the given clock cycle, and means, responsive to the scalar product signal, for generating the slope control signal, including filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal.

Claim 9

An apparatus responsive to a clock signal having serial clock cycles for reconstructing a first analog signal in response to digital signals including a plurality of digital outputs in serial clock cycles indicating a digital encoding of the first analog signal, comprising: integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, from n serial clock cycles, for generating an m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent; and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector, means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector and said m-dimensional weighting vector during the given clock cycle, and means, responsive to the scalar product signal, for generating the slope control signal, including filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal, wherein n is equal to 6 and m is equal to 3, and the digital outputs for the n serial clock cycles are defined as B 1 , B 2 , B 3 , B 4 , B 5 and B 6 ; and same m-dimensional vector is defined as C 1 , C 2 , and C 3 , where C 1 is true when B 1 through B 4 are equivalent, C 2 is true when B 1 through B 5 are equivalent and C 3 is true when B 1 through B 6 are equivalent; and wherein said means for storing an m-dimensional weighting vector stores a vector defined as W 1 , W 2 , and W 3 , where W 1 is equal to K, W 2 is equal to 2k, and W 3 is equal to 4k, where k is a preselected parameter; and wherein said means for generating a scalar product signal generates a signal which indicates the sum of C 1 W 1 +C 2 W 2 +C 3 W 3 during the given clock cycle.

Claim 10

An apparatus responsive to a clock signal having serial clock cycles for reconstructing a first analog signal in response to digital signals including a plurality of digital outputs in serial clock cycles indicating a digital encoding of the first analog signal, comprising: integrating means, responsive to a slope control signal and the digital outputs, for generating the reconstructed analog signal; and slope control means, responsive to the digital outputs, for generating the slope control signal in a given clock cycle, including means, responsive to n digital outputs B i , for i=1 to n, from n serial clock cycles, for generating an m-dimensional digital vector signal, where n and m are integers greater than one, and where said m-dimensional digital vector signal is defined as C j , for j=1 to (n-m), where C j is true when B 1 through B m+j are equivalent; and means, responsive to the m-dimensional digital vector signal, for generating the slope control signal for the given clock cycle, including means for storing an m-dimensional weighting vector, means for generating a scalar product signal indicating a scalar product of said m-dimensional digital vector and said m-dimensional weighting vector during the given clock cycle, and means, responsive to the scalar product signal, for generating the slope control signal, including filter means for low pass filtering the scalar product signal to generate a filtered scalar product signal, and converter means for logarithmically converting the filtered scalar product signal to generate the slope control signal, wherein n is equal to 6 and m is equal to 3, and the digital outputs for the n serial clock cycles are defined as B 1 , B 2 , B 3 , B 4 , B 5 and B 6 ; and same m-dimensional vector is defined as C 1 , C 2 , and C 3 , where C 1 is true when B 1 through B 4 are equivalent, C 2 is true when B 1 through B 5 are equivalent and C 3 is true when B 1 through B 6 are equivalent; and wherein said means for storing an m-dimensional weighting vector stores a vector defined as W 1 , W 2 , and W 3 , where W 1 is equal to K, W 2 is equal to 2k, and W 3 is equal to 4k, where k is a preselected parameter; and wherein said means for generating a scalar product signal generates a signal which indicates the sum of C 1 W 1 +C 2 W 2 +C 3 W 3 during the given clock cycle.

Claim 11

The apparatus of claims 1, 3, 4 or 6, wherein said filter means and said converter means provide a slope control signal characterized by a time constant of substantially six milliseconds