Encoding and decoding signals for transmission over a multi-access medium

Claim 3

Circuitry for decoding incoming channel frames, each of said frames composed of a plurality of data positions and having an embedded synchronizing signal comprising a signal in the first of said positions and no signal in the position corresponding to the midpoint of said positions, and data samples filling the remaining ones of said positions, said circuitry characterized by an interface circuit, coupled to said channel, for receiving and conditioning said frame data, a sampling signal generation circuit comprising a filter, coupled to said interface device, for providing a version of said synchronizing signal occurring at the frame rate, a frequency multiplier, coupled to said filter, for producing the data rate from said frame rate, a first limiter, coupled to said multiplier, for generating a first sequence of pulses at said data rate, a second limiter, coupled to said filter, for generating a second sequence of pulses at said frame rate, a counter, responsive to said first and second limiters, for supplying a set of pulses in correspondence to the number of said data positions, select logic circuitry, coupled to said counter, for producing a sampling signal corresponding to said remaining ones of said positions, and phase adjust circuitry, coupled to select logic, for positioning said sampling signal in essentially the midpoint of the associated data positions, and a sample-and-decision circuit, coupled to said phase-adjust circuit and said interface circuit, for sampling said incoming frames to produce said data samples.

Claim 4

Circuitry for decoding incoming channel frames, each of said frames composed of a plurality of data positions and having an embedded synchronizing signal comprising a signal in the first of said positions and no signal in the position corresponding to the midpoint of said positions, and data samples filling the remaining ones of said positions, said circuitry characterized by an interface circuit, coupled to said channel, for receiving and conditioning said frame data, a sampling signal generation circuit comprising a filter, coupled to said interface device, for providing a version of said synchronizing signal occurring at the frame rate, a frequency multiplier, coupled to said filter, for producing the data rate from said frame rate, a first limiter, coupled to said multiplier, for generating a first sequence of pulses at said data rate, a second limiter, coupled to said filter, for generating a second sequence of pulses at said frame rate, a counter, responsive to said first and second limiters, for supplying a set of pulses in correspondence to the number of said data positions, select logic circuitry, coupled to said counter, for producing a sampling signal corresponding to said remaining ones of said positions, and phase adjust circuitry, coupled to select logic, for positioning said sampling signal in essentially the midpoint of the associated data positions, and a sample-and-decision circuit, coupled to said phase-adjust circuit and said interface circuit, for sampling said incoming frames to produce said data samples.

Claim 5

A decoder for detecting data samples from incoming channel frames, each of said frames comprising four-bit positions wherein the first bit represents a logic one, the third bit represents a logic zero and the second and fourth bits contain contiguous ones of said data samples, said decoder comprising interface circuitry for receiving and processing said frames to produce a detected signal having a frequency component equal to the frame frequency, a resonant circuit, coupled to said interface circuitry, for filtering said detected signal to produce a first sinusoidal signal having a frequency equal to said frame frequency, a frequency doubler, coupled to said resonant circuit, for converting said first sinusoidal signal to a second sinusoidal signal having a frequency of twice said frame frequency, a phase adjuster, coupled to said doubler, for positioning the maxima of said second sinusoidal signal at essentially the midpoints of said second and fourth bit positions, a limiter, coupled to said phase adjuster, for converting said adjusted, second sinusoidal signal to a sampling signal for sampling said second and fourth bit positions, and sample and decision circuitry, responsive to said interface circuitry and said limiter, for sampling said detected signal with said sampling signal to produce said contiguous data samples.

Claim 6

A decoder for detecting data samples from incoming channel frames, each of said frames comprising four-bit positions wherein the first bit represents a logic one, the third bit represents a logic zero and the second and fourth bits contain contiguous ones of said data samples, said decoder comprising interface circuitry for receiving and processing said frames to produce a detected signal having a frequency component equal to the frame frequency, a resonant circuit, coupled to said interface circuitry, for filtering said detected signal to produce a first sinusoidal signal having a frequency equal to said frame frequency, a frequency doubler, coupled to said resonant circuit, for converting said first sinusoidal signal to a second sinusoidal signal having a frequency of twice said frame frequency, a phase adjuster, coupled to said doubler, for positioning the maxima of said second sinusoidal signal at essentially the midpoints of said second and fourth bit positions, a limiter, coupled to said phase adjuster, for converting said adjusted, second sinusoidal signal to a sampling signal for sampling said second and fourth bit positions, and sample and decision circuitry, responsive to said interface circuitry and said limiter, for sampling said detected signal with said sampling signal to produce said contiguous data samples.

Claim 7

In a system comprising a plurality of stations interconnected by a unidirectional medium, a method for communicating data frames over said medium, each of said frames composed of a plurality of bit positions, said method comprising the steps of designating the upstream station as a synchronizing station, generating within said synchronizing station and propagating over said medium a synchronizing waveform having a signal in the first of said positions and no signal in the midpoint of said positions, for the station gaining access to the medium, generating, in synchronism with said synchronizing waveform, pulses or no pulses in the remaining ones of said positions in correspondence to the data samples produced by said accessing station, within each of said stations, receiving and processing said data frames by filtering said incoming frames to produce a first sinusoid having a frequency given by the frame rate and by frequency multiplying said first sinusoid to produce a second sinusoid having a frequency given by the bit rate, and wherein said synchronizing waveform is derived from said first and second sinusoids, and generating a sampling waveform from said second sinusoid, said sampling waveform comprising sampling signals located at essentially the midpoints of all of said positions except the first position and the midpoint position, and sampling each of said frames with said sampling waveform to obtain said data samples propagated by said accessing station.

Claim 8

In a system comprising a plurality of stations interconnected by a unidirectional medium, a method for communicating data frames over said medium, each of said frames composed of a plurality of bit positions, said method comprising the steps of designating the upstream station as a synchronizing station, generating within said synchronizing station and propagating over said medium a synchronizing waveform having a signal in the first of said positions and no signal in the midpoint of said positions, for the station gaining access to the medium, generating, in synchronism with said synchronizing waveform, pulses or no pulses in the remaining ones of said positions in correspondence to the data samples produced by said accessing station, within each of said stations, receiving and processing said data frames by filtering said incoming frames to produce a first sinusoid having a frequency given by the frame rate and by frequency multiplying said first sinusoid to produce a second sinusoid having a frequency given by the bit rate, and wherein said synchronizing waveform is derived from said first and second sinusoids, and generating a sampling waveform from said second sinusoid, said sampling waveform comprising sampling signals located at essentially the midpoints of all of said positions except the first position and the midpoint position, and sampling each of said frames with said sampling waveform to obtain said data samples propagated by said accessing station.