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US4782460A Expired / Lapsed US ⏱️ 0.0 years remaining

Computing apparatus comprising a programmable resistor

Assignee: Nokia Bell Labs
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Filing: 1987-04-06
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Granted: 1988-11-01
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Expires: 2007-04-06
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Abstract

Abstract Computing apparatus (e.g., a neural network) advantageously comprises a programmable resistor body comprising typically a multiplicity of resistors R ij . The resistance of any given R ij is changeable from a relatively high resistance to a lower resistance by application of an appropriate electrical signal, and can be reset to a higher resistance by application of an appropriate signal of reverse polarity. Exemplarily, a programmable resistor body comprises a thin layer of bismuth oxide or strontium barium niobate.

Inventors

  • 👤 Edward G. Spencer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 11:29
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 312 words
Electronic computing apparatus comprising (a) a multiplicity of amplifier means, each one of the amplifier means having at least one input terminal and at least one output terminal; (b) means for electrically connecting the output terminal of any given amplifier means A j to the input terminal of at least one other amplifier means A i , the electrical connection having a predetermined resistance; (c) means for applying an electrical signal at least to the input terminal of one of the amplifier means; and (d) means that are responsive to the output signal of at least one of the amplifier means; characterized in that (e) the means of (b) comprise a programmable resistor body consisting substantially of a material having a state of relatively high resistivity and having a first and second major surface, a portion S i of the first surface being associated with A i and a portion S j of the second surface being associated with A j , associated with the programmable resistor body is a resistance R ij between S i and S j , the value of R ij being changeable from a relatively high value associated with the state of relatively high resistivity to a lower value by application of a "write" voltage between S i and S j , and the value of R ij being furthermore changeable from the lower value to a higher value by application of an "erase" voltage between S i and S j ; and (f) the apparatus further comprises means for applying the "write" voltage and the "erase" voltage between S i and S j , such that a predetermined resistance R ij can be formed between S i and S j , and such that the electrical connection of predetermined resistance between the input terminal of A i and the output terminal of A j is established.
Claim 2
Dependent Claim 312 words
Electronic computing apparatus comprising (a) a multiplicity of amplifier means, each one of the amplifier means having at least one input terminal and at least one output terminal; (b) means for electrically connecting the output terminal of any given amplifier means A j to the input terminal of at least one other amplifier means A i , the electrical connection having a predetermined resistance; (c) means for applying an electrical signal at least to the input terminal of one of the amplifier means; and (d) means that are responsive to the output signal of at least one of the amplifier means; characterized in that (e) the means of (b) comprise a programmable resistor body consisting substantially of a material having a state of relatively high resistivity and having a first and second major surface, a portion S i of the first surface being associated with A i and a portion S j of the second surface being associated with A j , associated with the programmable resistor body is a resistance R ij between S i and S j , the value of R ij being changeable from a relatively high value associated with the state of relatively high resistivity to a lower value by application of a "write" voltage between S i and S j , and the value of R ij being furthermore changeable from the lower value to a higher value by application of an "erase" voltage between S i and S j ; and (f) the apparatus further comprises means for applying the "write" voltage and the "erase" voltage between S i and S j , such that a predetermined resistance R ij can be formed between S i and S j , and such that the electrical connection of predetermined resistance between the input terminal of A i and the output terminal of A j is established.
Claim 3
Dependent Claim 36 words
Apparatus of claim 1, wherein the programmable resistor body is a relatively thin layer and wherein at least one of the first and second major surfaces is an interface between the layer and a layer-supporting substrate.
Claim 4
Dependent Claim 27 words
Apparatus of claim 1, wherein the material in the relatively high resistivity state has a resistivity that is greater than about 10 5 Ω-cm at room temperature.
Claim 5
Dependent Claim 21 words
Apparatus of claim 3, wherein at room temperature the maximum value of R ij is greater than about 10 10 Ω.
Claim 6
Dependent Claim 44 words
Apparatus of claim 1, wherein application of the "write" voltage comprises application of one or more voltage pulses of a given polarity, and wherein application of the "erase" voltage comprises application of one or more voltage pulses of polarity opposite to the given polarity.
Claim 7
Dependent Claim 46 words
Apparatus of claim 1, wherein the output terminal of substantially any given amplifier means A j is electrically connected to the input terminals of a multiplicity of amplifier means, with the given amplifier means A j optionally being a member of the multiplicity of amplifier means.
Claim 8
Dependent Claim 12 words
Apparatus of claim 1, wherein the apparatus is a neural network computer.
Claim 9
Dependent Claim 57 words
Apparatus of claim 1, wherein the material having a state of relatively high resistivity is selected from the class consisting of materials of nominal composition Bi 2 O 3 , Bi 12 GeO 20 , Bi 12 SiO 20 , Bi 4 Ge 3 O 12 , and Sr x Ba 1-x Nb 2 O 6 (0.5≦x≦0.7).
Claim 10
Dependent Claim 11 words
Apparatus of claim 8, wherein the material is slightly oxygen deficient.

References Cited (Backward Citations)

US4396998A Cited
US4518866A Cited
US4590589A Cited
US4660166A Cited
US4719591A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-11-01 1992-05-02 1992-11-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-11-01 1996-05-02 1996-11-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-11-01 2000-05-02 2000-11-01 $7700.00 Window Closed / Lapsed

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