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US4778641A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of molding a pin grid array package

Assignee: National Semiconductor Corp
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Filing: 1987-06-18
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Granted: 1988-10-18
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Expires: 2007-06-18
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Abstract

Abstract A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins. The other flat-faced mold platen contains molding cavities that are in registry with and slightly larger than the PW boards. The mold cavities include a series of ribs that are distributed around the cavity periphery. These ribs bear against the PW board when the mold is assembled so that the PW board is centered and pressed against the flat face of first platen in the region outboard of the pin-grid pattern. When a liquified plastic encapsulant is forced into the mold the cavities will be filled and the liquid will be excluded from the pin side of the PW board.

Inventors

  • 👤 Chok J. Chia

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 19:25
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49146

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 204 words
A process for packaging a semiconductor device pin-grid array comprising the steps: providing a plurality of printed wiring boards each one having a plurality of pins extending from one face thereof in pin-grid array form, a semiconductor device secured to the opposing face and means for connecting said pins to the bonding pads on said semiconductor device; locating said printed wiring boards within a mold having a first platen with a flat face and cut out regions in said flat face to accommodate said pins and a second platen having a flat face with cavities therein slightly larger than said printed wiring boards; providing ribs around the periphery of said cavities which bear against the edges of said printed wiring boards to locate said printed wiring boards within said cavities and to press said printed wiring boards against said flat face of said first platen; pressing said first and second platens together so that their flat faces mate so as to locate said cavities in registry with said cut-outs and said printed wiring boards; transferring a quantity of liquidized encapsulant into said cavities to encapsulate said printed wiring boards; curing said encapsulant, at least in part; and removing said encapsulated packages from said mold.
Claim 2
Dependent Claim 204 words
A process for packaging a semiconductor device pin-grid array comprising the steps: providing a plurality of printed wiring boards each one having a plurality of pins extending from one face thereof in pin-grid array form, a semiconductor device secured to the opposing face and means for connecting said pins to the bonding pads on said semiconductor device; locating said printed wiring boards within a mold having a first platen with a flat face and cut out regions in said flat face to accommodate said pins and a second platen having a flat face with cavities therein slightly larger than said printed wiring boards; providing ribs around the periphery of said cavities which bear against the edges of said printed wiring boards to locate said printed wiring boards within said cavities and to press said printed wiring boards against said flat face of said first platen; pressing said first and second platens together so that their flat faces mate so as to locate said cavities in registry with said cut-outs and said printed wiring boards; transferring a quantity of liquidized encapsulant into said cavities to encapsulate said printed wiring boards; curing said encapsulant, at least in part; and removing said encapsulated packages from said mold.
Claim 3
Dependent Claim 32 words
The process of claim 1 wherein said curing step involves a partial encapsulant cure and the cure is completed by a heating step after said encapsulated packages are removed from said mold.
Claim 4
Dependent Claim 34 words
The process of claim 1 wherein the step of providing ribs includes providing rib extensions that bear against the edges of said printed wiring boards so as to precisely locate them in said mold.

References Cited (Backward Citations)

US3449641A Cited
US4480975A Cited
US4491556A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-18 1992-04-18 1992-10-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-18 1996-04-18 1996-10-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-18 2000-04-18 2000-10-18 $7700.00 Window Closed / Lapsed

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