US4777624A
Expired / Lapsed
US
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Dynamic memory device
Assignee: Fujifilm Business Innovation Corp
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Filing: 1986-07-11
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Granted: 1988-10-11
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Expires: 2006-07-11
Abstract
Abstract A dynamic memory device comprises a dynamic memory circuit, an input buffer circuit for temporarily storing data each time it is received from a source external to the device; an output buffer circuit for temporarily storing data each time it is read out from the dynamic memory circuit and for outputting the stored data in a unit of a predetermined number of words each time a request for reading is made; and a control circuit for controlling the input and output buffer circuits so that reading and writing operations can be performed independently of a refreshing operation.
Inventors
- 👤 Hiroaki Ishizawa
- 👤 Hisao Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:31
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
225 words
A dynamic memory device comprising: (a) a dynamic memory circuit having a memory capacity of a predetermined number of words; (b) a first buffer circuit for temporarily storing data each time it is supplied from a source external to said device; (c) a second buffer circuit for temporarily storing data each time it is read out from said dynamic memory circuit, and for outputting said stored data in a unit of a predetermined number of words each time a request for reading said data is made from a remote location; (d) an input words number detecting circuit for detecting the fact that the number of words stored in said first buffer circuit reaches a predetermined number; (e) a read words number detecting circuit for detecting the fact that the number of words read out from said second buffer circuit reaches a predetermined number; and (f) a control circuit for controlling writing of said data stored in said first buffer circuit into said dynamic memory circuit when a detected signal is input from said input words number detecting circuit, for controlling reading of said data from said dynamic memory circuit when a detected signal is input from said rad words number detecting circuit, and for controlling refreshing of said dynamic memory circuit with a predetermined word unit each time said data is written or read out.
Claim 2
Dependent Claim
225 words
A dynamic memory device comprising: (a) a dynamic memory circuit having a memory capacity of a predetermined number of words; (b) a first buffer circuit for temporarily storing data each time it is supplied from a source external to said device; (c) a second buffer circuit for temporarily storing data each time it is read out from said dynamic memory circuit, and for outputting said stored data in a unit of a predetermined number of words each time a request for reading said data is made from a remote location; (d) an input words number detecting circuit for detecting the fact that the number of words stored in said first buffer circuit reaches a predetermined number; (e) a read words number detecting circuit for detecting the fact that the number of words read out from said second buffer circuit reaches a predetermined number; and (f) a control circuit for controlling writing of said data stored in said first buffer circuit into said dynamic memory circuit when a detected signal is input from said input words number detecting circuit, for controlling reading of said data from said dynamic memory circuit when a detected signal is input from said rad words number detecting circuit, and for controlling refreshing of said dynamic memory circuit with a predetermined word unit each time said data is written or read out.
Claim 3
Dependent Claim
25 words
The dynamic memory device as set forth in claim 1, wherein the first and second buffer circuits respectively comprise a first-in first-out type buffer memory.
Claim 4
Dependent Claim
104 words
The dynamic memory device as set forth in claim 1, wherein: the memory capacity of said first buffer circuit and said second buffer circuit, and the number of words detected by said input words number detecting circuit and said read words number detecting circuit, are so determined that a period of time for generating a detected output signal from said input words number detecting circuit or said read words number detecting circuit is longer than an average period of time for writing data from said external source or reading out said data by at least a period of time required for said refreshing operation.
Claim 5
Dependent Claim
23 words
The dynamic memory device as set forth in claim 1, wherein said dynamic memory circuit is composed of "n" sets of dynamic circuits.
Claim 6
Dependent Claim
41 words
The dynamic memory device as set forth in claim 4, wherein said first and second buffer circuits are respectively composed of "n" sets of circuits which are arranged so as to correspond to said "n" sets of said dynamic memory circuit.
Claim 7
Dependent Claim
66 words
The dynamic memory device as set forth in claim 1, wherein: said dynamic circuit comprises a shift register having a memory capacity of "m" bits, said register having serial-in/serial-out terminals and parallel-in/parallel-out terminals, and "m" sets of dynamic memory elements, so that the access speed for said dynamic memory elements is reduced to 1/m of the writing speed of said data received from said external source.
Claim 8
Dependent Claim
47 words
The dynamic memory device as set forth in claim 4, wherein: data to be written from said external source is composed of "n" bits per word and data of each bit is written into each of said "n" sets of said dynamic memory circuits one by one.
Claim 9
Dependent Claim
38 words
The dynamic memory device as set forth in claim 4, wherein each bit of one word data composed of "n" bits written in each dynamic memory circuit is read out one by one from each dynamic memory circuit.
Claim 10
Dependent Claim
29 words
The dynamic memory device as set forth in claim 1, wherein said first buffer circuit and said second buffer circuit share a single buffer circuit in a time-sharing manner.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-11 | 1992-04-11 | 1992-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-11 | 1996-04-11 | 1996-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-11 | 2000-04-11 | 2000-10-11 | $7700.00 | Window Closed / Lapsed |