High speed successive approximation register in analog-to-digital converter

Claim 2

An N-bit successive approximation register comprising in combination: (a) an N-bit latch including N latch bit circuits each having an output, a latching input, and a data input coupled to a comparison data conductor conducting a signal indicative of whether a prior successive approximation number is too high or too low; (b) N gating means each having a first input coupled to an output of a respective latch bit circuit, a second input, and an output for producing a bit of an N-bit successive approximation number; (c) an N-bit shift register including N shift register bit circuits, each having an output coupled to the second input of a respective gating means and a latching input of a respective latch bit circuit, and a shift input coupled to a clock conductor; and (d) means for writing a first logic level into a most significant one of the shift register bit circuits, a second logic level opposite to the first into the remaining shift register bits circuits, the outputs of the N gating means sequentially producing N N-bit successive approximation numbers as the first logic level is shifted through the shift register bit circuits in response to certain edges of a clock signal on the clock conductor.

Claim 3

A successive approximation method for converting an analog signal to a digital signal, the method comprising the steps of: (a) providing i. an MSB latch and a plurality of latches, ii. an MSB shift register bit and a plurality of shift register bits, iii. a plurality of gates each having an output coupled to a respective input of a digital-to-analog converter; (b) storing a first logic level in each of the latches, a second logic level in each of the shift register bits, and storing a third logic level in the MSB shift register bits, the third logic level being opposite to the second logic level; (c) operating one of the gates in response to the third logic level in the MSB shift register bit to produce a fourth logic level on the output of that gate, and operating the remaining gates in response to the second logic levels in the remaining shift register bits to produce a fifth logic level opposite to the fourth logic level on the outputs of those gates, respectively, to thereby produce a first digital approximation number on the outputs of the gates; (d) operating the digital-to-analog converter to produce an output signal and comparing the output signal to an input signal representative of the analog signal, and producing a comparison signal indicative of whether the output signal is greater or less than the input signal; (e) latching the level of the comparison signal into the MSB latch and shifting the third logic level in the MSB shift register bit to a next most significant shift register bit in response to a clock signal; (f) operating another of the gates in response to the third logic level in the next most significant shift register bit to produce the fourth logic level on the output of that gate; (g) repeating step (d); (h) latching the level of the comparison signal into the next most significant latch and shifting the third logic level to a next most significant shift register bit in response to the clock signal; and (i) repeating steps (f)-(h) for all remaining shift register bits and latches in order of decreasing significance, to thereby provide in the MSB latch and the plurality of latches the digital signal as an accurate digital representation of the analog signal.

Claim 4

A successive approximation method for converting an analog signal to a digital signal, the method comprising the steps of: (a) providing i. an MSB latch and a plurality of latches, ii. an MSB shift register bit and a plurality of shift register bits, iii. a plurality of gates each having an output coupled to a respective input of a digital-to-analog converter; (b) storing a first logic level in each of the latches, a second logic level in each of the shift register bits, and storing a third logic level in the MSB shift register bits, the third logic level being opposite to the second logic level; (c) operating one of the gates in response to the third logic level in the MSB shift register bit to produce a fourth logic level on the output of that gate, and operating the remaining gates in response to the second logic levels in the remaining shift register bits to produce a fifth logic level opposite to the fourth logic level on the outputs of those gates, respectively, to thereby produce a first digital approximation number on the outputs of the gates; (d) operating the digital-to-analog converter to produce an output signal and comparing the output signal to an input signal representative of the analog signal, and producing a comparison signal indicative of whether the output signal is greater or less than the input signal; (e) latching the level of the comparison signal into the MSB latch and shifting the third logic level in the MSB shift register bit to a next most significant shift register bit in response to a clock signal; (f) operating another of the gates in response to the third logic level in the next most significant shift register bit to produce the fourth logic level on the output of that gate; (g) repeating step (d); (h) latching the level of the comparison signal into the next most significant latch and shifting the third logic level to a next most significant shift register bit in response to the clock signal; and (i) repeating steps (f)-(h) for all remaining shift register bits and latches in order of decreasing significance, to thereby provide in the MSB latch and the plurality of latches the digital signal as an accurate digital representation of the analog signal.

Claim 5

In an analog-to-digital converter, a successive approximation register comprising in combination: (a) a plurality of data latches, including a most significant data latch, each having a data input coupled to a comparison data conductor, a latching input, and an output; (b) a plurality of master-slave shift register bit circuits, including a first shift register bit circuit, each having a clock input coupled to a clock signal conductor and each having an output and a data input; (c) a plurality of gating circuits each having a first input, and each also having a second input coupled to the output of a respective one of the data latches, and an output conducting a respective bit of a digital approximation number to an input of a digital-to-analog converter; (d) a plurality of means for coupling the output of each shift register bit circuit to both the latching input of a corresponding data latch and the first input of a corresponding gating circuit, respectively; and (e) means for setting a first logical level in the first shift register bit circuit and a second logic level opposite to the first in the other shift register bit circuits, and means for setting a third logic level in all of the data latches except the first data latch, whereby the first level set in the first shift register bit circuit propagates through the other shift register bit circuits in response to the clock signal, causing the gating circuits to produce a plurality of binary successive approximation numbers by producing a fourth logic level having a preselected relationship to the third logic level on successively less significant inputs of the digital-to-analog converter, the transitions of the first logic level to the second logic level as the first logic level propagates causing latching of comparison data on the comparison data conductor into corresponding data latches.

Claim 6

In an analog-to-digital converter, a successive approximation register comprising in combination: (a) a plurality of data latches, including a most significant data latch, each having a data input coupled to a comparison data conductor, a latching input, and an output; (b) a plurality of master-slave shift register bit circuits, including a first shift register bit circuit, each having a clock input coupled to a clock signal conductor and each having an output and a data input; (c) a plurality of gating circuits each having a first input, and each also having a second input coupled to the output of a respective one of the data latches, and an output conducting a respective bit of a digital approximation number to an input of a digital-to-analog converter; (d) a plurality of means for coupling the output of each shift register bit circuit to both the latching input of a corresponding data latch and the first input of a corresponding gating circuit, respectively; and (e) means for setting a first logical level in the first shift register bit circuit and a second logic level opposite to the first in the other shift register bit circuits, and means for setting a third logic level in all of the data latches except the first data latch, whereby the first level set in the first shift register bit circuit propagates through the other shift register bit circuits in response to the clock signal, causing the gating circuits to produce a plurality of binary successive approximation numbers by producing a fourth logic level having a preselected relationship to the third logic level on successively less significant inputs of the digital-to-analog converter, the transitions of the first logic level to the second logic level as the first logic level propagates causing latching of comparison data on the comparison data conductor into corresponding data latches.

Claim 7

An N-bit successive approximation register comprising in combination: (a) an N-bit latch including N latch bit circuits each having an output, a latching input, and a data input coupled to a comparison data conductor conducting a signal indicative of whether a prior successive approximation number is too high or too low; (b) N gating means each having a first input coupled to an output of a respective latch bit circuit, a second input, and an output for producing a bit of an N-bit successive approximation number; (c) an N-bit shift register including N shift register bit circuits, each having an output coupled to the second input of a respective gating means and a latching input of a respective latch bit circuit, and a shift input coupled to a clock conductor; and (d) means for writing a first logic level into a most significant one of the shift register bit circuits, a second logic level opposite to the first into the remaining shift register bits circuits, and a third logic level into each of the latch bit circuits except a most significant one, the outputs of the N gating means sequentially producing N N-bit successive approximation numbers as the first logic level is shifted through the shift register bit circuits in response to certain edges of a clock signal on the clock conductor.

Claim 8

An N-bit successive approximation register comprising in combination: (a) an N-bit latch including N latch bit circuits each having an output, a latching input, and a data input coupled to a comparison data conductor conducting a signal indicative of whether a prior successive approximation number is too high or too low; (b) N gating means each having a first input coupled to an output of a respective latch bit circuit, a second input, and an output for producing a bit of an N-bit successive approximation number; (c) an N-bit shift register including N shift register bit circuits, each having an output coupled to the second input of a respective gating means and a latching input of a respective latch bit circuit, and a shift input coupled to a clock conductor; and (d) means for writing a first logic level into a most significant one of the shift register bit circuits, a second logic level opposite to the first into the remaining shift register bits circuits, and a third logic level into each of the latch bit circuits except a most significant one, the outputs of the N gating means sequentially producing N N-bit successive approximation numbers as the first logic level is shifted through the shift register bit circuits in response to certain edges of a clock signal on the clock conductor.

Claim 9

The N-bit successive approximation register of claim 4 wherein each of the shift register bit circuits includes a edgeclocked master-slave flip-flop and each latch bit circuit includes a single level latched single state flip-flop.

Claim 10

The N-bit successive approximation register of claim 4 wherein each of the gating means performs a logical ANDing function.

Claim 11

The N-bit successive approximation register of claim 6 wherein the third logic level is a "0", and a sequence of successive approximation numbers produced by the N-bit successive approximation register is 100 . . . 0, X10 . . . .0, . . . , X . . . X1, XX . . . X wherein the X's designate binary "1's" and "0's" representative of N successive levels of the signal on the comparison data signal conductor.

Claim 12

The N-bit successive approximation register of claim 6 wherein the third logic level is a "1", and a sequence of successive approximation numbers produced by the N-bit successive approximation register is 011 . . . 1, X01 . . . 1, X . . . X0, XX . . . X wherein the X's designate binary "1's" and "0's" representative of N successive levels of the signal on the comparison data signal conductor.

Claim 13

The N-bit successive approximation register of claim 6 wherein each gating means includes a two input AND gate.

Claim 14

The N-bit successive approximation register of claim 9 wherein the first input of each AND gate is coupled to the Q output of a corresponding latch bit circuit.

Claim 15

The N-bit successive approximation register of claim 6 wherein each gating means includes a two input NAND gate.

Claim 16

The N-bit successive approximation register of claim 11 wherein the first input of each NAND gate is coupled to a Q * output of a corresponding latch bit circuit.

Claim 17

The N-bit successive approximation register of claim 12 wherein each latch bit circuit except one corresponding to a most significant bit of the successive approximation register includes a first CMOS transmission gate coupled between the data input of that latch bit circuit and a first conductor thereof, a first CMOS NAND gate having a first input coupled to the first conductor, a second input coupled to the writing means and an output coupled to the Q * output of that latch bit circuit, a CMOS inverter having an output and also having an input coupled to the Q * output, and a second CMOS transmission gate coupled between the output of the CMOS inverter and the first conductor.