Frequency multiplying circuit

Claim 1

A frequency multiplying circuit comprising: input terminal means for receiving an input pulse signal having HIGH and LOW logic levels; first time counting means, responsive to the received input pulse signals and a reference timing signal, for producing a first detection signal when the HIGH levels of the input pulse signals are longer than a predetermined length determined by said reference timing signal; second time counting means, responsive to the received input pulse signals and said reference timing signal, for producing a second detection signal when the LOW levels of the input pulse signals are longer than a predetermined length determined by said reference timing signal; gate timing determination means, responsive to said first detection signal and to said second detection signal, for providing a gate signal in response to said first detection signal, and for providing another gate signal in response to said second detection signal; first pulse generating means, responsive to one of said gate signals and said received input signal, for detecting a rising edge of said input pulse signals, and for generating first pulses in response to the detected rising edge; second pulse generating means, responsive to another one of said gate signals and said received input signals, for detecting a falling edge of said input pulse signals, and for generating second pulses in response to the detected falling edge; output means, for receiving said first and second pulses, and for providing a frequency multiplied output of said input pulse signals based on said first and second pulses; whereby the frequency multiplication of said input pulse signals is prohibited when the frequency of said input pulse signals is higher than a predetermined frequency.