Patent US4777391A successfully refreshed from Google Patents.
US4777391A
Expired / Lapsed
US
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Bipolar multiplexer having a select buffer circuit with a charging and discharging circuit
Assignee: Signetics Corp
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Filing: 1987-07-17
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Granted: 1988-10-11
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Expires: 2007-07-17
Abstract
Abstract A select buffer circuit includes a first inverter circuit, a second inverter circuit connected to the first, and a circuit for charging and discharging the base of an inverter transistor in the second inverter circuit from a node in the first inverter circuit. The charging and discharging circuit includes a Schottky diode connected to the inverter transistor, a Schottky transistor connected in series with the diode, and a resistor for coupling the base of the Schottky transistor to the node in the first inverter circuit. A bipolar multiplexer including the select buffer circuit offers the advantage of an improved output waveform.
Inventors
- 👤 Yong-In Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04126; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K19/00; H03K19/003; H03K19/00346; H03K19/00353
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
323 words
A select buffer circuit for use in a bipolar multiplexer, which comprises: a first inverter circuit having a select input terminal, first and second bipolar phase-splitter transistors, a first bipolar inverter transistor, and an inverting output terminal, the bases of said first and second phase-splitter transistors being connected together and coupled to said select input terminal, the emitters of said first and second phase-splitter transistors being connected together, the collector of said second phase-splitter transistor being coupled to said inverting output terminal, the base of said first inverter transistor being connected to the emitters of said first and second phase-splitter transistors, the collector of said first inverter transistor being connected to said inverting output terminal, and the emitter of said first inverter transistor being connected to ground; a second inverter circuit having an input, a third bipolar phase-splitter transistor, and a noninverting output terminal, the input of said second inverter circuit being connected to the collector of said first phase-splitter transistor and the base of said third phase-splitter transistor, and a second bipolar inverter transistor, the base of said second inverter transistor being connected to the emitter of said third phase-splitter transistor, the collector of said second inverter transistor being connected to said noninverting output terminal and the emitter of said second inverter transistor being connected to ground; a voltage supply line, the collectors of said first, second and third phase-splitter transistors and said first and second inverter transistors being coupled to said supply line; and circuit means for controlling the charging and discharging of the base of said second inverter transistor and comprising a Schottky diode having its anode connected to the base of said second inverter transistor, a Schottky discharging transistor having its collector connected to the cathode of said diode and its emitter connected to ground, and a resistor, said resistor being connected between the base of said discharging transistor and the emitters of said first and second phase-splitter transistors.
Claim 2
Dependent Claim
323 words
A select buffer circuit for use in a bipolar multiplexer, which comprises: a first inverter circuit having a select input terminal, first and second bipolar phase-splitter transistors, a first bipolar inverter transistor, and an inverting output terminal, the bases of said first and second phase-splitter transistors being connected together and coupled to said select input terminal, the emitters of said first and second phase-splitter transistors being connected together, the collector of said second phase-splitter transistor being coupled to said inverting output terminal, the base of said first inverter transistor being connected to the emitters of said first and second phase-splitter transistors, the collector of said first inverter transistor being connected to said inverting output terminal, and the emitter of said first inverter transistor being connected to ground; a second inverter circuit having an input, a third bipolar phase-splitter transistor, and a noninverting output terminal, the input of said second inverter circuit being connected to the collector of said first phase-splitter transistor and the base of said third phase-splitter transistor, and a second bipolar inverter transistor, the base of said second inverter transistor being connected to the emitter of said third phase-splitter transistor, the collector of said second inverter transistor being connected to said noninverting output terminal and the emitter of said second inverter transistor being connected to ground; a voltage supply line, the collectors of said first, second and third phase-splitter transistors and said first and second inverter transistors being coupled to said supply line; and circuit means for controlling the charging and discharging of the base of said second inverter transistor and comprising a Schottky diode having its anode connected to the base of said second inverter transistor, a Schottky discharging transistor having its collector connected to the cathode of said diode and its emitter connected to ground, and a resistor, said resistor being connected between the base of said discharging transistor and the emitters of said first and second phase-splitter transistors.
Claim 3
Dependent Claim
22 words
A select buffer circuit as in claim 1, wherein said resistor has a value of between about 30 ohms and 100 ohms.
Claim 4
Dependent Claim
18 words
A select buffer circuit as in claim 2, wherein said resistor has a value of about 60 ohms.
Claim 5
Dependent Claim
111 words
A bipolar multiplexer comprising a select buffer circuit as in claim 1, 2 or 3, further comprising a first AND gate having a first input connected to the inverting output terminal of said first inverter circuit, a second input connected to a first multiplexer input terminal, and an output; a second AND gate having a first input connected to the noninverting output terminal of said second inverter circuit, a second input connected to a second multiplexer input terminal, and an output; and an OR gate having a first input connected to said first AND gate output, a second input connected to said second AND gate output, and a multiplexer output terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-11 | 1992-04-11 | 1992-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-11 | 1996-04-11 | 1996-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-11 | 2000-04-11 | 2000-10-11 | $7700.00 | Window Closed / Lapsed |