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Patent US4775954A successfully refreshed from Google Patents.
US4775954A
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Apparatus for generating timing signals used for testing ICs having two enable input terminals
Assignee: Ando Electric Co Ltd
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Filing: 1986-09-29
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Granted: 1988-10-04
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Expires: 2006-09-29
Abstract
Abstract A timing signal generating apparatus is used for testing ICs, particularly ICs having more than two enable input terminals. Data representative of the time of occurrence of a timing signal with respect to a reference signal is stored in a memory. In a first cycle, data is combined by an arithmetic unit with data stored in another memory. The latter data represents a predetermined desired variation in the time of occurrence of the timing signal. The output of the arithmetic unit is then stored in a temporary memory and combined with the data representative of the predetermined variation in time of occurrence of the timing signal. The time of occurrence of the timing signal is determined by the output of the arithmetic unit. A timing signal is thus produced over an almost arbitrary range of delays with respect to the reference signal.
Inventors
- 👤 Takanori Fujieda
- 👤 Tadatoshi Miyagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:57
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
171 words
A timing signal generating apparatus for producing timing signals asynchronously with respect to reference signals, comprising: a signal generator for producing a reference signal; a controller for generating a controller command; a first memory for storing data; a temporary memory for storing data; a selector for selecting either said data stored in said first memory or said data stored in said temporary memory based on said controller command; a second memory for storing data; an arithmetic unit for combining data stored in said second memory with data selected by said selector and for producing an arithmetic output representative of the combination thereof; said temporary memory being coupled to said arithmetic unit so as to store said arithmetic output; and a counter for receiving said arithmetic output and for counting to a value represented by said arithmetic output in response to said reference signal and for producing a timing signal with a delay relative to said reference signal which corresponds to the time required for said counter to count to said value.
Claim 2
Dependent Claim
171 words
A timing signal generating apparatus for producing timing signals asynchronously with respect to reference signals, comprising: a signal generator for producing a reference signal; a controller for generating a controller command; a first memory for storing data; a temporary memory for storing data; a selector for selecting either said data stored in said first memory or said data stored in said temporary memory based on said controller command; a second memory for storing data; an arithmetic unit for combining data stored in said second memory with data selected by said selector and for producing an arithmetic output representative of the combination thereof; said temporary memory being coupled to said arithmetic unit so as to store said arithmetic output; and a counter for receiving said arithmetic output and for counting to a value represented by said arithmetic output in response to said reference signal and for producing a timing signal with a delay relative to said reference signal which corresponds to the time required for said counter to count to said value.
Claim 3
Dependent Claim
18 words
A timing signal generating apparatus according to claim 1, wherein said arithmetic unit is constituted by an adder.
Claim 4
Dependent Claim
18 words
A timing signal generating apparatus according to claim 1, wherein said arithmetic unit is constituted by a subtractor.
References Cited (Backward Citations)
US3952253A
Cited
US4131855A
Cited
US4306190A
Cited
US4523289A
Cited
GB2070827A
Cited
US4450560A
Cited
US4555663A
Cited
US4584683A
Cited
US4573175A
Cited
JPS6067869A
Cited
JPS6096023A
Cited
JPS6175615A
Cited
EP0208049A2
Cited
US4680479A
Cited
US4719375A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |