US4775930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic key check for ensuring proper cradles insertion by respective processing board
Assignee: Bombardier Transportation Holdings USA Inc
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Filing: 1985-11-12
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Granted: 1988-10-04
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Expires: 2005-11-12
Abstract
Abstract Keying check apparatus is provided for a control system including at least two microprocessor cradles, with each microprocessor cradle having a unique control program, and which keying check apparatus determines through operation with one of a first and second interrupt that the desired control program and the correct connections are provided for the CPU board of each microprocessor cradle.
Inventors
- 👤 Keith W. Clawson
- 👤 Richard D. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/006; G06F11/30; G06F11/32; G06F11/324; G06F11/325
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
215 words
A microprocessor system having: at least a first microprocessor cradle and a second microprocessor cradle; a first CPU board having first CPU means applying a first key signal to first cradle wiring when said first board is inserted in a first designated slot in said first cradle for electrical connections including connection to said first cradle wiring; a second CPU board having second CPU means applying a second key signal to second cradle wiring when said second board is inserted in a second designated slot in said second cradle for electrical connections including connection to said second cradle wiring; said first CPU means having first key control means responsive to a first interrupt signal generated by said first CPU board in response only to said first key signal to make said first CPU board operational if said first CPU is inserted in said first slot in said first cradle and connected to said first cradle wiring; and said second CPU means having second key control means responsive to a second interrupt signal generated by said second CPU board in response only to said second key signal to make said second CPU board operational if said second CPU board is inserted in said second slot in said second cradle and connected to said second cradle wiring.
Claim 2
Dependent Claim
215 words
A microprocessor system having: at least a first microprocessor cradle and a second microprocessor cradle; a first CPU board having first CPU means applying a first key signal to first cradle wiring when said first board is inserted in a first designated slot in said first cradle for electrical connections including connection to said first cradle wiring; a second CPU board having second CPU means applying a second key signal to second cradle wiring when said second board is inserted in a second designated slot in said second cradle for electrical connections including connection to said second cradle wiring; said first CPU means having first key control means responsive to a first interrupt signal generated by said first CPU board in response only to said first key signal to make said first CPU board operational if said first CPU is inserted in said first slot in said first cradle and connected to said first cradle wiring; and said second CPU means having second key control means responsive to a second interrupt signal generated by said second CPU board in response only to said second key signal to make said second CPU board operational if said second CPU board is inserted in said second slot in said second cradle and connected to said second cradle wiring.
Claim 3
Dependent Claim
39 words
The control apparatus of claim 1, with the first control means being a first software program operating with the first CPU means, and with the second control means being a second software program operating with the second CPU means.
Claim 4
Dependent Claim
63 words
The control apparatus of claim 1, with the first CPU means including a first digital output connected to a first interrupt control circuit of said first CPU board for providing the first interrupt signal, and with the second CPU means including a second digital output connected to a second interrupt control circuit of said second CPU board for providing the second interrupt signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |