US4775809A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer circuit avoiding electrostatic breakdown
Assignee: Sony Corp
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Filing: 1987-06-01
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Granted: 1988-10-04
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Expires: 2007-06-01
Abstract
Abstract This invention relates to an output buffer circuit that improves the electrostatic sustenance. In the circuit construction of the present invention there are provided dummy MOS transistors that are connected to an output terminal in parallel with the standard MOS transistors for an output buffer, and which are not connected to an input terminal. Due to circuit construction, the dummy transistors increase the capacity of the buffer circuit and an output buffer circuit which has high electrostatic breakdown can be obtained.
Inventors
- 👤 Kazuo Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
143 words
A circuit comprising, an input terminal, a first PMOS transistor which has a source, drain and gate and its gate connected to said input terminal, a first NMOS transistor which has a source, drain and gate and its gate connected to said input terminal, a voltage source connected to the source of said first PMOS transistor, a reference potential connected to the source of said first NMOS transistor, a second PMOS transistor which has a source, drain and gate and its source and drain connected together and the combination connected to said voltage source, a second NMOS transistor which has a source, drain and gate and its source and gate connected together and to said reference potential, and an output terminal connected to the drains of said first and second PMOS transistors and to the drains of said first and second NMOS transistors.
Claim 2
Dependent Claim
143 words
A circuit comprising, an input terminal, a first PMOS transistor which has a source, drain and gate and its gate connected to said input terminal, a first NMOS transistor which has a source, drain and gate and its gate connected to said input terminal, a voltage source connected to the source of said first PMOS transistor, a reference potential connected to the source of said first NMOS transistor, a second PMOS transistor which has a source, drain and gate and its source and drain connected together and the combination connected to said voltage source, a second NMOS transistor which has a source, drain and gate and its source and gate connected together and to said reference potential, and an output terminal connected to the drains of said first and second PMOS transistors and to the drains of said first and second NMOS transistors.
Claim 3
Dependent Claim
28 words
A circuit according to claim 1 including a sense amplifier which receives at its input signals from memory cell devices and supplies its output to said input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |