Dual block still video compander processor

Claim 2

A still video transceiver, comprising: a digital video frame store memory adaptable to store plural blocks of video data; a dual port memory having first and second memory ports; means for fetching dual blocks of video data from said frame store memory and for loading said dual blocks into said dual port memory; digital signal processor means for accessing through said first memory port and discrete cosine transforming each one of said dual blocks to generate a corresponding block of transform coefficients; data processing means for accessing through said second port and compressing each block of said transform coefficients to generate a batch of compressed transform coefficients therefrom, whereby said digital signal processing means and said data processing means may operate virtually simultaneously upon different respective ones of said dual blocks.

Claim 3

The video transceiver of claim 1 wherein said the individual transform coefficients in said batch of compressed transform coefficients are of various bit-lengths, said transceiver further comprising temporary buffer means for queuing said compressed transform coefficients into an uninterrupted continuum of bits, so as to enable continuous byte-by-byte writing of said data into said compressed image buffer.

Claim 4

The video transceiver of claim 1 wherein said dual port memory further comprises means for storing a pair of key values at a pair of key locations individually associated with said pair of blocks, and wherein said digital signal processing means further comprises means for changing one of said key values to a predetermined value whenever said digital signal processing means has processed the corresponding one of said blocks, and wherein said data processing means comprises means for changing one of said key location values to another preselected value whenever the corresponding one of said blocks has been processed by said data processing means, and wherein each of said processing means fetches a given one of said dual blocks from said dual port memory only when the corresponding key location value equals a predetermined value, so as to assure that said blocks are processed in the proper sequence.

Claim 5

The video transceiver of claim 1 wherein said data processing means performs minimum redundancy encoding and wherein said transceiver further comprises the following compression processing means which are allocated among said compression processing means and said digital signal processing means: (a) means for rearranging the data of each of said blocks of transform coefficients into serial order; (b) means for discarding those of said coefficients whose amplitude lies below a predetermined threshold value; and (c) means for normalizing and quantizing each of said coefficients.

Claim 6

The still video transceiver of claim 1 further comprising a serial port connected to an external personal computer, said serial port comprising means permitting said external computer to fetch and store image data in said image buffer and compressed image data in said compressed image buffer, and to control said data processing means.

Claim 7

The video transceiver of claim 1 further comprising serial port controller means characterized by a transmission mode and a receive mode, for receiving data from said compression buffer and transmitting it over an external channel in said transmission mode, and for receiving data from said external channel for storage in said compression buffer in said receiving mode.

Claim 8

The video transceiver of claim 6 further comprising a modem connected at the interface between said serial port controller means and said external channel, said modem being adapted to provide low bandwidth data rates characteristic of dial-up telephone transmission lines and the like.

Claim 9

The video transceiver of claim 1 wherein said frame store includes an image buffer and a compressed image buffer, wherein said transceiver has two operational modes, namely a transmission mode wherein data from said compressed image buffer is unloaded and transmitted over a narrow band channel, and a receiving mode wherein data is received from said narrow band channel and stored in said compressed image buffer, and wherein said dual block grabbing means grabs said dual blocks from said image buffer during said transmission mode and grabs said dual blocks from said compressed image buffer in said receiving mode.

Claim 10

The video transceiver of claim 8 wherein said data processing means comprises: (a) means for rearranging the data of each of said blocks of transform coefficients into a serial array of said transform coefficients; (b) means for discarding those of said coefficients whose amplitude lies below a predetermined threshold value; (c) means for normalizing and quantizing each of said coefficients; and (d) means for minimum redundancy encoding said coefficients.

Claim 11

The video transceiver of claim 9 wherein said data processor means is further adapted to perform the inverse functions of said rearranging means, thresholding means, normalization and quantization means and said minimum redundancy encoding means whenever said video transceiver operates in said receiving mode.

Claim 12

In a video transceiver including a frame store memory having an image buffer for storing uncompressed image data and a compressed buffer for storing compressed image data, said video transceiver adapted to receive and transmit compressed video data over an external channel in a receive mode and a transmit mode, respectively, a parallel image processor comprising: a dual port memory having first and second ports and means for storing rectangular blocks of video data obtained from said frame store memory and means for storing key values associated with each one of said pair of blocks; data processing means acting through one of said first and second ports for grabbing a pair of blocks from either of said image buffer or said compressed image buffer and storing said pair of blocks in said dual port memory, and changing said key values to a first value; transforming means acting through said first port for transforming, in accordance with a discrete cosine transform algorithm, one of said blocks stored in said dual port memory to generate a block of transform coefficients therefrom; and encoding means acting through said second port for minimum redundancy encoding the other of said blocks stored on said dual port memory to generate a corresponding batch of compressed transformed coefficients, and then changing the corresponding one of said key values to a second value, wherein said encoding means and said transforming means are each responsive, whenever one of said location values equals a respective one of said first and second values, for accessing the corresponding one of said two blocks in said dual port memory, whereby said transforming means and said encoding means are mutually prevented from accessing out of order one of said blocks from said dual port memory.

Claim 13

In a video transceiver including a frame store memory having an image buffer for storing uncompressed image data and a compressed buffer for storing compressed image data, said video transceiver adapted to receive and transmit compressed video data over an external channel in a receive mode and a transmit mode, respectively, a parallel image processor comprising: a dual port memory having first and second ports and means for storing rectangular blocks of video data obtained from said frame store memory and means for storing key values associated with each one of said pair of blocks; data processing means acting through one of said first and second ports for grabbing a pair of blocks from either of said image buffer or said compressed image buffer and storing said pair of blocks in said dual port memory, and changing said key values to a first value; transforming means acting through said first port for transforming, in accordance with a discrete cosine transform algorithm, one of said blocks stored in said dual port memory to generate a block of transform coefficients therefrom; and encoding means acting through said second port for minimum redundancy encoding the other of said blocks stored on said dual port memory to generate a corresponding batch of compressed transformed coefficients, and then changing the corresponding one of said key values to a second value, wherein said encoding means and said transforming means are each responsive, whenever one of said location values equals a respective one of said first and second values, for accessing the corresponding one of said two blocks in said dual port memory, whereby said transforming means and said encoding means are mutually prevented from accessing out of order one of said blocks from said dual port memory.

Claim 14

The video transceiver of claim 11 wherein said frame store includes an image buffer and a compressed image buffer, wherein said transceiver has two operational modes, namely a transmission mode wherein data from said compressed image buffer is unloaded and transmitted over a narrow band channel, and a receiving mode wherein data is received from said narrow band channel and stored in said compressed image buffer, and wherein said dual block grabbing means grabs said dual blocks from said image buffer during said transmission mode and grabs said dual blocks from said compressed image buffer in said receiving mode.

Claim 15

The video transceiver of claim 11 wherein the individual transform coefficients in said batch of compressed transform coefficients are of various bit-lengths, said transceiver further comprising temporary buffer means for queuing said compressed transform coefficients into an uninterrupted continuum of bits, so as to enable continuous byte-by-byte writing of said data into said compressed image buffer.

Claim 16

The video transceiver of claim 11 wherein said dual port memory further comprises means for storing a pair of key value at a pair of key locations individually associated with said pair of blocks, and wherein said transforming means further comprises means for changing one of said key values to a predetermined value whenever said transforming means has transformed the corresponding one of said blocks, and wherein said encoding means comprises means for changing one of said key location values to another preselected value whenever the corresponding one of said blocks has been encoded by said encoding means, and wherein each of said processing means fetches a given one of said dual blocks from said dual port memory only when the corresponding key location value equals a respective one of said predetermined values, so as to assure that said blocks are processed in the proper sequence.

Claim 17

The video transceiver of claim 11 wherein said data processing means includes said encoding means and wherein said transceiver further comprises the following compression processing means which are allocated among said data processing means and said transforming means: (a) means for rearranging each of said blocks of transform coefficients into serial order; (b) means for discarding those of said transform coefficients whose amplitude lies below a predetermined threshold value; and (c) means for normalizing and quantizing each of said transform coefficients.

Claim 18

The video transceiver of claim 11 wherein said encoding means further comprises: (a) means for rearranging the data of each of said blocks of transform coefficients into a serial array of said transform coefficients; (b) means for discarding those of said coefficients whose amplitude lies below a predetermined threshold value; and (c) means for normalizing and quantizing each of said coefficients.

Claim 19

The video transceiver of claim 16 wherein said transforming means and said encoding means are adapted to perform the inverse of their respective functions whenever said video transceiver operates in said receive mode.

Claim 20

The video transceiver of claim 11 further comprising serial port controller means for receiving data from said compressed buffer and transmitting it over said external channel in said transmission mode, and for receiving data from said external channel for storage in said compressed buffer in said receiving mode.

Claim 21

The video transceiver of claim 18 further comprising a modem connected at the interface between said serial port controller means and said external channel, said modem being adapted to provide low bandwidth data rates.

Claim 22

The still video transceiver of claim 11 further comprising a serial port connectable to an external personal computer, said serial port comprising means permitting said external computer to fetch and store image data in said image buffer and compressed image data in said compressed image buffer, and to control said data processing means.

Claim 23

The video transceiver of claim 10 or 20 further comprising a second video transceiver connectable to said external channel having a second serial port connectable to a second external personal computer, whereby to provide a still video personal computer network.