Patent US4771455A successfully refreshed from Google Patents.
US4771455A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scrambling apparatus
Assignee: Sony Corp
•
Filing: 1983-04-28
•
Granted: 1988-09-13
•
Expires: 2003-04-28
Abstract
Abstract The present invention relates to a scrambling apparatus and particularly to a scrambling apparatus in which a scrambling signal is inserted into a main signal in a predetermined period (period of duration during which the main signal is not damaged) of the main signal which makes a dummy signal. According to an embodiment of the present invention, there is provided a scrambling apparatus which comprises a detecting circuit (36) for detecting that the level of the above main signal becomes lower than a predetermined value and an adding circuit (25) for adding the above main signal and the scrambling signal whereby the supply of the above scrambling signal to the adding circuit (25) is stopped by the output from the detecting circuit (36) to prevent the scrambled signal from being leaked. The scrambling apparatus of the invention can be applied to an interphone and the like.
Inventors
- 👤 Nobuo Hareyama
- 👤 Mitsuo Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:59
CPC Classifications
H; H04; H04K; H04K1/00; H04K1/10; H04K1/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
156 words
A scrambling apparatus in which portions of a signal (fc) to be scrambled are inserted at predetermined intervals into an intelligence signal (fd), said signal (fc) to be scrambled and said intelligence signal being in the form of analog signals, said apparatus comprising an A/D converter (32) for analog-to-digital (A/D) converting said signal (fc) to be scrambled, a synchronizing signal source producing a synchronizing signal (f cl ), a D/A converter (34) for digital-to-analog (D/A) converting the output data from said A/D converter at every said predetermined interval in synchronism with said synchronizing signal (f cl ), an adding circuit (26) supplied with said intelligence signal (fd) and the analog output signal from said D/A converter, and detecting means for detecting when said intelligence signal (fd) falls below a predetermined level and for preventing insertion of said signal (fc) to be scrambled into said intelligence signal (fd) while said intelligence signal (fd) remains below said level.
Claim 2
Dependent Claim
156 words
A scrambling apparatus in which portions of a signal (fc) to be scrambled are inserted at predetermined intervals into an intelligence signal (fd), said signal (fc) to be scrambled and said intelligence signal being in the form of analog signals, said apparatus comprising an A/D converter (32) for analog-to-digital (A/D) converting said signal (fc) to be scrambled, a synchronizing signal source producing a synchronizing signal (f cl ), a D/A converter (34) for digital-to-analog (D/A) converting the output data from said A/D converter at every said predetermined interval in synchronism with said synchronizing signal (f cl ), an adding circuit (26) supplied with said intelligence signal (fd) and the analog output signal from said D/A converter, and detecting means for detecting when said intelligence signal (fd) falls below a predetermined level and for preventing insertion of said signal (fc) to be scrambled into said intelligence signal (fd) while said intelligence signal (fd) remains below said level.
Claim 3
Dependent Claim
54 words
A scrambling apparatus according to claim 1 wherein data provided by A/D-converting said signal (fc) to be scrambled are stored in a random access memory 30, and upon reading said stored data a portion of said signal (fc) to be scrambled corresponding to a predeterminedd interval and to said synchronizing f cl is D/A-converted.
Claim 4
Dependent Claim
24 words
A scrambling apparatus according to claim 2 wherein said data provided by A/D-converting said signal (fc) to be scrambled are re-arranged on a timebase.
Claim 5
Dependent Claim
41 words
A scrambling apparatus according to claim 1 wherein said adding circuit (26) is supplied with said signal (fd), said signal (fc) to be scrambled and said sychronizing signal f cl of a frequency corresponding to the frequency of said predetermined intervals.
References Cited (Backward Citations)
US2129860A
Cited
US3406344A
Cited
US3714622A
Cited
US3921151A
Cited
US4340906A
Cited
US4336554A
Cited
US4336554B1
Cited
US4392021A
Cited
US4434323A
Cited
EP0087565A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |