Output stage current limit circuit

Claim 2

An amplifier output stage comprising: first output transistor means having a base, an emitter and a collector for controlling current flow; first current mirror transistor means connected in parallel to the first output transistor means for providing a first mirrored collector current which is a function of collector current of the first output transistor means; means for producing a first voltage which is a function of the first mirrored collector current; and first current limit transistor means connected to the base of the first output transistor means for controlling base current to the first output transistor means as a function of the first voltage to limit the collector current of the first output transistor means.

Claim 3

The amplifier output stage of claim 1 wherein the means for producing a first voltage comprises: current mirror means for mirroring the first mirrored collector current; and resistor means connected to the current mirror means for producing the first voltage as a function of current flowing therethrough.

Claim 4

The amplifier output stage of claim 1 and further comprising: an output terminal; first and second power supply terminals; and wherein the first output transistor means has its emitter and collector connected in a current path between the first power supply terminal and the output terminal.

Claim 5

The amplifier output stage of claim 3 and further comprising: second output transistor means for controlling current flow and having a base and having an emitter and a collector connected in a current path between the output terminal and the second power supply terminal; second current mirror transistor means connected in parallel to the second output transistor means for providing a second mirrored collector current which is a function of the collector current of the second output transistor means; means for producing a second voltage which is a function of the second mirrored collector current; and second current limit transistor means connected to the base of the second output transistor means for controlling base current to the second output transistor means as a function of the second voltage to limit the collector current of the second output transistor means.

Claim 6

The amplifier output stage of claim 4 wherein the first and second output transistor means and the first and second current mirror transistor means are bipolar transistors of first conductivity type.

Claim 7

The amplifier output stage of claim 5 wherein the first and second current limit transistor means are bipolar transistors of the first conductivity type.

Claim 8

The amplifier output stage of claim 5 wherein the first conductivity type is NPN.

Claim 9

An amplifier output stage comprising: first and second power supply terminals; an output terminal; a current source circuit connected between the first power supply terminal and the output terminal for sourcing a first current to the output terminal, the current source circuit including a first output transistor having a base and having an emitter-collector current path through which the first current flows; a current sink circuit connected between the second power supply terminal and the output terminal for sinking a second current from the output terminal, the current sink circuit including a second output transistor having a base and having an emitter-collector current path through which the second current flows; a first current limit circuit for limiting the first current including a first current sensing transistor connected in parallel to the first output transistor for producing a first mirror current which is a function of the first current; means for producing a first voltage as a function of the first mirror current; and means for controlling base current of the first output transistor as a function of the first voltage; and a second current limit circuit for limiting the second current including a second current sensing transistor connected in parallel to the second output transistor for producing a second mirror current which is a function of the second current; means for producing a second voltage as a function of the second mirror current; and means for controlling base current of the second output transistor as a function of the second voltage.

Claim 10

An amplifier output stage comprising: first and second power supply terminals; an output terminal; a current source circuit connected between the first power supply terminal and the output terminal for sourcing a first current to the output terminal, the current source circuit including a first output transistor having a base and having an emitter-collector current path through which the first current flows; a current sink circuit connected between the second power supply terminal and the output terminal for sinking a second current from the output terminal, the current sink circuit including a second output transistor having a base and having an emitter-collector current path through which the second current flows; a first current limit circuit for limiting the first current including a first current sensing transistor connected in parallel to the first output transistor for producing a first mirror current which is a function of the first current; means for producing a first voltage as a function of the first mirror current; and means for controlling base current of the first output transistor as a function of the first voltage; and a second current limit circuit for limiting the second current including a second current sensing transistor connected in parallel to the second output transistor for producing a second mirror current which is a function of the second current; means for producing a second voltage as a function of the second mirror current; and means for controlling base current of the second output transistor as a function of the second voltage.

Claim 11

The amplifier output stage of claim 8 wherein the first and second output transistors and the first and second current sensing transistors are NPN transistors.

Claim 12

The amplifier output stage of claim 9 wherein the means for controlling base current of the first output transistor and the means for controlling base current of the second output transistor comprise NPN transistors.