Patent US4771227A successfully refreshed from Google Patents.
US4771227A
Expired / Lapsed
US
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Output impedance compensation circuit
Assignee: Analog Devices International ULC
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Filing: 1986-11-19
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Granted: 1988-09-13
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Expires: 2006-11-19
Abstract
Abstract A circuit is provided for reducing the output impedance of an emitter-follower transistor in which a positive feedback voltage proportional to the collector current of the emitter-follower transistor is provided to the base of the emitter-follower transistor when the emitter-follower transistor supplies current to a load. The circuit includes a resistor-ratioed current source which provides collector current to the emitter-follower transistor and which forces a current through a resistor connected to the base of the output transistor in proportion to the collector current.
Inventors
- 👤 Carl T. Nelson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:50
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
205 words
A circuit for biasing a transistor connected as an emitter-follower, the emitter-follower transistor having an output impedance and a collector, an emitter and a base, the circuit comprising: a first terminal for connection to a first supply of voltage and a second terminal for connection to a second supply of voltage; means for supplying current from the first terminal to the collector of the emitter-follower transistor, said current supply means including a first transistor having a collector, and emitter and a base; means connected to the second terminal for applying a bias voltage to the base of the emitter-follower transistor; and means connected to said current supply means, to said bias voltage means, and to said second terminal for sensing the magnitude of current supplied to the collector of the emitter-follower transistor and responsively increasing the bias voltage when the collector current conducted by the emitter-follower transistor increases, said current sensing means including a second transistor having a collector, an emitter and a base, said second transistor having a polarity complementary to the polarity of said first transistor, whereby substantially all of the current conducted by the emitter-follower transistor is drawn from the first terminal and the output impedance of the emitter-follower transistor is reduced.
Claim 2
Dependent Claim
205 words
A circuit for biasing a transistor connected as an emitter-follower, the emitter-follower transistor having an output impedance and a collector, an emitter and a base, the circuit comprising: a first terminal for connection to a first supply of voltage and a second terminal for connection to a second supply of voltage; means for supplying current from the first terminal to the collector of the emitter-follower transistor, said current supply means including a first transistor having a collector, and emitter and a base; means connected to the second terminal for applying a bias voltage to the base of the emitter-follower transistor; and means connected to said current supply means, to said bias voltage means, and to said second terminal for sensing the magnitude of current supplied to the collector of the emitter-follower transistor and responsively increasing the bias voltage when the collector current conducted by the emitter-follower transistor increases, said current sensing means including a second transistor having a collector, an emitter and a base, said second transistor having a polarity complementary to the polarity of said first transistor, whereby substantially all of the current conducted by the emitter-follower transistor is drawn from the first terminal and the output impedance of the emitter-follower transistor is reduced.
Claim 3
Dependent Claim
23 words
The circuit of claim 1, wherein the polarity of said first transistor is npn, and the polarity of said second transistor is pnp.
Claim 4
Dependent Claim
40 words
The circuit of claim 1, further comprising: means for connecting the base-emitter junctions of said first and second transistors serially in a loop, such that said second transistor conducts a current directly proportional to current supplied by said first transistor.
Claim 5
Dependent Claim
81 words
The circuit of claim 3, wherein said connecting means comprises: a first resistor connected between the base of said first transistor and the emitter of said second transistor; and a second resistor connected between the base of said second transistor and the emitter of said first transistor; and wherein: the ratio of the current conducted by said second transistor to the current conducted by said first transistor is approximately equal to the ratio of said first resistor to said second resistor.
Claim 6
Dependent Claim
58 words
The circuit of claim 1 or claim 3, wherein said means for applying a bias voltage comprises: a voltage divider means having a node for producing an intermediate voltage which is less than the voltage at the second terminal; and means for applying at least a portion of the intermediate voltage to the base of the emitter-follower transistor.
Claim 7
Dependent Claim
25 words
The circuit of claim 5, wherein said intermediate voltage applying means comprises a resistor connected between the node and the base of the emitter-follower transistor.
Claim 8
Dependent Claim
21 words
The circuit of claim 1, wherein the voltage at the first terminal is greater than the voltage at the second terminal.
Claim 9
Dependent Claim
177 words
A circuit for biasing a transistor connected as an emitter-follower, the emitter-follower transistor having an output impedance and a collector, an emitter and a base, the circuit comprising: a first supply terminal for connection to a first voltage, and a second supply terminal for connection to a second voltage; means for applying a bias voltage to the base of the emitter-follower transistor; an npn transistor having a collector connected to draw current from said first terminal, a base connected to draw current from said second terminal, and an emitter connected to supply its emitter current to the collector of the emitter-follower transistor; and a pnp transistor having a collector connected to the base of the emitter-follower transistor, an emitter, and a base; wherein: the base-emitter circuits of said first and second transistors are connected serially in a loop such that a compensating voltage is applied to the base of the emitter-follower transistor which increases in response to increased current conducted by the collector of the emitter-follower transistor, whereby the output impedance of the emitter-follower transistor is reduced.
Claim 10
Dependent Claim
177 words
A circuit for biasing a transistor connected as an emitter-follower, the emitter-follower transistor having an output impedance and a collector, an emitter and a base, the circuit comprising: a first supply terminal for connection to a first voltage, and a second supply terminal for connection to a second voltage; means for applying a bias voltage to the base of the emitter-follower transistor; an npn transistor having a collector connected to draw current from said first terminal, a base connected to draw current from said second terminal, and an emitter connected to supply its emitter current to the collector of the emitter-follower transistor; and a pnp transistor having a collector connected to the base of the emitter-follower transistor, an emitter, and a base; wherein: the base-emitter circuits of said first and second transistors are connected serially in a loop such that a compensating voltage is applied to the base of the emitter-follower transistor which increases in response to increased current conducted by the collector of the emitter-follower transistor, whereby the output impedance of the emitter-follower transistor is reduced.
Claim 11
Dependent Claim
22 words
The circuit of claim 8, wherein substantially all of the current conducted by the emitter-follower transistor is drawn from said first terminal.
Claim 12
Dependent Claim
21 words
The circuit of claim 9, wherein the voltage at said first terminal is greater than the voltage at said second terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |