High speed multiplier

Claim 1

A high speed multiplier circuit for performing multiplication of first and second numbers stored in first and second registers respectively, comprising: a recoding means; means for generating a clock signal at a frequency equal to an even multiple of a system clock frequency to provide a plurality of clock pulses within each system clock cycle; means connected to said second register for selectively gating a selective portion of said second number stored in said second register to said recoding means at a rate equal to an even multiple of said system clock frequency under the control of said means for generating a clock signal; shift gate means connected to outputs of said first register and controlled by control signal outputs of said recoding means to output selected groups of bits at a rate equal to an even multiple of said system clock frequency under the control of said means for generating a clock signal; adder means connected to outputs of said shift gate means, for adding a group of multiples of said first number, under the control of said control signals and for generating output signals from said adder means; spill adder means, connected to outputs of said adder means for generating a low order portion of a final result of said multiplication; storage means for storing said low order portion of said final result; means for generating a high order portion of said final result from outputs of said adder means; and means for storing said high order portion of said final result such that such final result is stored at least in a first half of said system clock cycle to increase the speed of operation of said multiply circuit.

Claim 6

A method for multiplying first and second multibit numbers, each comprising one or more multibit digits, stored in first and second registers, comprising the steps of: generating a clock signal at a frequency equal to an even multiple of a system clock frequency to provide additional clocking pulses in a system clock cycle to speed the operation of said method for multiplying; recoding a predetermined portion of said second number; generating a plurality of control signals from said recoded portion of said second number; controlling the selection of a plurality of multiples of said first number by said control signals; adding, in an adder means a group of said multiples of said first number under the control of said control signals at a clock rate controlled by said generated even multiple clock signal; accumulating successive products generated by said adding steps; spilling a low order portion of said accumulated products to a spill adder on each cycle of said multiply operation to generate a low order portion of a final result of said multiply; storing said low order portion of said final result in a low order result register; repeating said above steps on successive portions of said second number until all bits in said second number have been processed by the above steps; and storing a final accumulated product in a result register as a high order portion of said final result of said multiply of said first and second numbers.

Claim 7

A method for multiplying first and second multibit numbers, each comprising one or more multibit digits, stored in first and second registers, comprising the steps of: generating a clock signal at a frequency equal to an even multiple of a system clock frequency to provide additional clocking pulses in a system clock cycle to speed the operation of said method for multiplying; recoding a predetermined portion of said second number; generating a plurality of control signals from said recoded portion of said second number; controlling the selection of a plurality of multiples of said first number by said control signals; adding, in an adder means a group of said multiples of said first number under the control of said control signals at a clock rate controlled by said generated even multiple clock signal; accumulating successive products generated by said adding steps; spilling a low order portion of said accumulated products to a spill adder on each cycle of said multiply operation to generate a low order portion of a final result of said multiply; storing said low order portion of said final result in a low order result register; repeating said above steps on successive portions of said second number until all bits in said second number have been processed by the above steps; and storing a final accumulated product in a result register as a high order portion of said final result of said multiply of said first and second numbers.