← Back to Patent Explorer
US4768035A Expired / Lapsed US ⏱️ 0.0 years remaining

Coherent radar digital data collector and sampling technique for noncoherent transmitter radars

Assignee: Johns Hopkins University
•
Filing: 1985-04-18
•
Granted: 1988-08-30
•
Expires: 2005-04-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A Radar Digital Data Processor has been developed which produces I (phase) and Q (quadrature) data obtained by sampling the receiver IF of a radar with a single A/D converter. A sampling technique was developed for this application to allow operation with radars employing a noncoherent transmitter such as a magnetron. Representative field results are presented employing spectral analysis proving the viability of the sampling technique for Doppler processing.

Inventors

  • 👤 Robert E. Thurber
  • 👤 Richard J. Prengaman
  • 👤 Joe Phipps
  • 👤 Russell Rzemien

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 09:35
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S13/52; G01S13/522; G01S13/524; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/288

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 283 words
A processor for extracting Doppler data from a noncoherent radar system having a return signal receiver producing an intermediate frequency (IF) signal, the processor comprising: one analog to digital (A/D) converter means for converting samples obtained from the IF signal to digital values; one sample and hold circuit means connected to said A/D converter means and the return signal receiver, wherein said sample and hold circuit means in response to timing signals precisely phased locked to a transmitted pulse of the radar system samples the IF signal at two points separated by 90 electrical degrees in order to obtain an in-phase (I) data sample and quadrature (Q) data sample, said sample and hold circuit means temporarily holds the I and Q samples and provides the I and Q samples to said A/D converter means; moving target indication (MTI) filtering means connected to the A/D converter means for receiving and filtering the digital values representing the I and Q samples output by the A/D converter means; timing means connected to the sample and hold circuit means and the A/D converter means and the MTI filtering means, wherein said system timing means provides timing signals precisely phase locked to a transmitted pulse of the radar system to said sample and hold circuit means and said A/D converter means for controlling the sampling and A/D conversion of the IF signal and said timing means provides timing signals precisely phase locked to a transmitted pulse of the radar system to said MTI filtering means for regulating the filtering of the I and Q samples; and detector means connected to said timing means for precisely phase locking said timing means to a transmitted pulse of the radar system.
Claim 2
Dependent Claim 283 words
A processor for extracting Doppler data from a noncoherent radar system having a return signal receiver producing an intermediate frequency (IF) signal, the processor comprising: one analog to digital (A/D) converter means for converting samples obtained from the IF signal to digital values; one sample and hold circuit means connected to said A/D converter means and the return signal receiver, wherein said sample and hold circuit means in response to timing signals precisely phased locked to a transmitted pulse of the radar system samples the IF signal at two points separated by 90 electrical degrees in order to obtain an in-phase (I) data sample and quadrature (Q) data sample, said sample and hold circuit means temporarily holds the I and Q samples and provides the I and Q samples to said A/D converter means; moving target indication (MTI) filtering means connected to the A/D converter means for receiving and filtering the digital values representing the I and Q samples output by the A/D converter means; timing means connected to the sample and hold circuit means and the A/D converter means and the MTI filtering means, wherein said system timing means provides timing signals precisely phase locked to a transmitted pulse of the radar system to said sample and hold circuit means and said A/D converter means for controlling the sampling and A/D conversion of the IF signal and said timing means provides timing signals precisely phase locked to a transmitted pulse of the radar system to said MTI filtering means for regulating the filtering of the I and Q samples; and detector means connected to said timing means for precisely phase locking said timing means to a transmitted pulse of the radar system.
Claim 3
Dependent Claim 25 words
A processor according to claim 1, the MTI filtering means comprising first and second MTI filtering means for respectively receiving the I and Q samples.
Claim 4
Dependent Claim 14 words
A processor as in claim 2, comprising a transmitter coupled to a local oscillator.
Claim 5
Dependent Claim 66 words
A processor according to claim 2, the timing means for controlling the sampling and A/D conversion of the IF signal and regulating the filtering of the I and Q samples said timing means comprising an A/D timing means which is connected to said sample and hold circuit means and said A/D converter means and a system timing means which is connected to said MTI filtering means.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-08-30 1992-02-29 1992-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-08-30 1996-02-29 1996-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-08-30 2000-02-29 2000-08-30 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag