US4766268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Board for printed circuits and processes for manufacturing such printed boards
Assignee: US Philips Corp
•
Filing: 1987-03-19
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Granted: 1988-08-23
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Expires: 2007-03-19
Abstract
Abstract A printed circuit board, in which the substrate (1) and interconnections (2) are masked by a solder-resistant lacquer mask consisting of two layers of lacquer (4,5), the lands (3) being left unmasked, one layer of lacquer (4), which extends to the edges of the lands (3) and directly masks the substrate (1), is provided at least in the region of the lands (3), and the other layer of lacquer (5) masks the interconnections (2), while leaving the lands (3) unmasked, and extends to the region occupied by the layer of lacquer (4) extending to the edges of the lands (3) the two layers overlapping.
Inventors
- 👤 Werner Uggowitzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:24
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H05K1/00; H05K1/02; H05K1/11; H05K1/111; H05K2203/00; H05K2203/05; H05K2203/0562; H05K2203/0588; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
141 words
A printed circuit board comprising electrical interconnections and solder lands provided in the form of electrically conductive sections on a substrate comprising a board of insulating material and a solder-resistant lacquer mask, consisting of two lacquer layers masking the substrate and the interconnections but not the lands, one of said lacquer layers at least partially covering the other lacquer layer, characterized in that one of said lacquer layers directly masks the substrate and extends to the edges of the electrically conductive sections, at least in the region adjacent to the lands while leaving the lands, uncovered and said other lacquer layer masks the interconnections, extends to the region occupied by the lacquer layer extending to the edges of the electrically conductive sections and leaves the lands uncovered, said lacquer layers overlapping at least at the edges of said electrically conductive sections.
Claim 2
Dependent Claim
141 words
A printed circuit board comprising electrical interconnections and solder lands provided in the form of electrically conductive sections on a substrate comprising a board of insulating material and a solder-resistant lacquer mask, consisting of two lacquer layers masking the substrate and the interconnections but not the lands, one of said lacquer layers at least partially covering the other lacquer layer, characterized in that one of said lacquer layers directly masks the substrate and extends to the edges of the electrically conductive sections, at least in the region adjacent to the lands while leaving the lands, uncovered and said other lacquer layer masks the interconnections, extends to the region occupied by the lacquer layer extending to the edges of the electrically conductive sections and leaves the lands uncovered, said lacquer layers overlapping at least at the edges of said electrically conductive sections.
Claim 3
Dependent Claim
42 words
A printed circuit board as claimed in claim 1, characterized in that the lacquer layer extending to the edges of the electrically conductive sections extensively masks the substrate and is extensively covered by the other lacquer layer, the lands being left uncovered.
Claim 4
Dependent Claim
45 words
A printed circuit board as claimed in claim 1, characterized in that the lacquer layer (5) which leaves the lands uncovered and masks the interconnections and the substrate at least partially covers the lacquer layer (4) extending to the edges of the electrically conductive sections.
Claim 5
Dependent Claim
181 words
A process for manufacturing a printed circuit board comprising a substrate comprising a board of insulating material, desired electrical conductive interconnections and lands in the form of electrically conductive sections provided on said substrate and a solder-resistant lacquer mask masking the interconnections and the substrate but not the lands, said process comprising, after providing the interconnections and lands on the substrate, applying to the substrate and the interconnections at least in the region of the lands, a first lacquer layer (4), and which adheres only to the substrate, hardening said first lacquer layer, removing said first hardened lacquer layer from said lands and interconnections by chemical means, applying a second solder-resistant lacquer layer (5), said second lacquer layer adheres to said substrate, to said interconnections and to said lands to partially cover the interconnections, and said hardened first lacquer layer, at least in the region of said lands, so as to leave the lands partially uncovered and spaced from the substrate, hardening said second solder-resist solder lacquer and then completing the manufacture of the printed circuit board in the usual manner.
Claim 6
Dependent Claim
181 words
A process for manufacturing a printed circuit board comprising a substrate comprising a board of insulating material, desired electrical conductive interconnections and lands in the form of electrically conductive sections provided on said substrate and a solder-resistant lacquer mask masking the interconnections and the substrate but not the lands, said process comprising, after providing the interconnections and lands on the substrate, applying to the substrate and the interconnections at least in the region of the lands, a first lacquer layer (4), and which adheres only to the substrate, hardening said first lacquer layer, removing said first hardened lacquer layer from said lands and interconnections by chemical means, applying a second solder-resistant lacquer layer (5), said second lacquer layer adheres to said substrate, to said interconnections and to said lands to partially cover the interconnections, and said hardened first lacquer layer, at least in the region of said lands, so as to leave the lands partially uncovered and spaced from the substrate, hardening said second solder-resist solder lacquer and then completing the manufacture of the printed circuit board in the usual manner.
Claim 7
Dependent Claim
36 words
The process as claimed in claim 4, characterized in that after the chemical removal of the first lacquer layer (4) from the electrically conductive sections the remaining portion of the first lacquer layer is hardened again.
Claim 8
Dependent Claim
173 words
A process for the manufacture of a printed circuit comprising a substrate comprising a board of insulating material, desired electrical interconnecting and lands in the form of electrically conductive sections provided on said substrate and a solder-resistant lacquer mask masking the interconnections and the substrate but not the lands, said process comprising, after providing the interconnections and lands on the substrate, applying to the substrate and the interconnections a first lacquer layer which layer adheres to said substrate, said interconnections and said lands while leaving the lands unmasked and separated from said substrate by said first lacquer layer, hardening said first lacquer layer, applying to any unmasked parts of said substrate, to at least part of said hardened first lacquer layer and to said lands a second solder-resistant lacquer layer (7) which adheres only to said substrate and to said hardened first lacquer layer, hardening said second lacquer layer, removing said second lacquer layer from said lands by chemical means and completing the manufacture of the printed circuit board in the usual means.
Claim 9
Dependent Claim
173 words
A process for the manufacture of a printed circuit comprising a substrate comprising a board of insulating material, desired electrical interconnecting and lands in the form of electrically conductive sections provided on said substrate and a solder-resistant lacquer mask masking the interconnections and the substrate but not the lands, said process comprising, after providing the interconnections and lands on the substrate, applying to the substrate and the interconnections a first lacquer layer which layer adheres to said substrate, said interconnections and said lands while leaving the lands unmasked and separated from said substrate by said first lacquer layer, hardening said first lacquer layer, applying to any unmasked parts of said substrate, to at least part of said hardened first lacquer layer and to said lands a second solder-resistant lacquer layer (7) which adheres only to said substrate and to said hardened first lacquer layer, hardening said second lacquer layer, removing said second lacquer layer from said lands by chemical means and completing the manufacture of the printed circuit board in the usual means.
Claim 10
Dependent Claim
34 words
The process as claimed in claim 6, characterized in that after the chemical removal of the second lacquer layer (5) from the lands the remaining portions of the second lacquer layer is again hardened.
References Cited (Backward Citations)
DE1187282B
Cited
US4064287A
Cited
US4088828A
Cited
US4104111A
Cited
US4220810A
Cited
US4390615A
Cited
US4413309A
Cited
US4479983A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-23 | 1992-02-22 | 1992-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-23 | 1996-02-22 | 1996-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-23 | 2000-02-22 | 2000-08-23 | $7700.00 | Window Closed / Lapsed |