Bit slice - type arithmetic adder circuit using exclusive-or logic for use with a look-ahead circuit

Claim 2

An adder circuit for connection to a source of input signals and a source of external carry signals comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means connected to receive the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n in accordance with the following logical formula: G.sub.2n+1 =A.sub.2n+1 B.sub.2n+1 +(A.sub.2n+1 ⊕B.sub.2n+1)·A.sub.2n B.sub.2n P.sub.2n+1 =(A.sub.2n+1 ⊕B.sub.2n+1)·(A.sub.2n ⊕B.sub.2n) X.sub.2n+1 =A.sub.2n+1 ⊕B.sub.2n+1 X.sub.2n =A.sub.2n ⊕B.sub.2n Y.sub.2n =A.sub.2n ·B.sub.2n Wherein 2n=0, 2, 4, . . . , (M-1) and 2n+1, 3, . . . , M and (b) said third circuit means includes an Exclusive-OR circuit which receives one corresponding output X i from said first circuit means and the internal carry signal C i from a corresponding unit of said second circuit means so as to produce the sum signal S i for the addition of said first and second binary signals for the i th bit position thereof, said sum signal S i being expressed by the following logical formula: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 3

An adder circuit as claimed in claim 1, wherein said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula: ##EQU4## wherein C 0 =C 1N =G -1 and C 1 =Y 0 +X 0 C 1N .

Claim 4

An adder circuit as claimed in claim 2, wherein the second circuit means produce a carry generate signal G and a carry propagate signal P of the following logical formula: G=G.sub.2n+1 +P.sub.2n+1 G.sub.2n-1 +P.sub.2n+1 P.sub.2n-1 G.sub.2n-3 + . . . +P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.5 P.sub.3 G.sub.1 P=P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.3 P.sub.1.

Claim 5

An adder circuit as claimed in claim 2, wherein each of said arithmetic and logical circuits includes AND gates and OR gates which are constituted of current mode transistor switching circuits and which assembled to receive input signals A 2n+1 , A 2n , B 2n+1 and B 2n so as to generate five outputs G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n .

Claim 6

An adder circuit as claimed in claim 2, wherein said first circuit means includes a plurality of arithmetic and logic arrays, each of which includes a current mode switching type transistor logic circuit having four switching type transistor logic circuits having four inputs for receiving the input bit signals A 2n+1 , A 2n , B 2n+1 , B 2n and five outputs for outputting the X 2n , X 2n+1 , Y 2n , G 2n+1 and P 2n+1 , the current mode switching type transistor logic circuit including: a first emitter-coupled transistor logic receiving the inputs A 2n and B 2n to provide through a first emitter follower a logical product A 2n .B 2n ; a second emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n and B 2n to output through a second emitter follower an exclusive logic sum A 2n ⊕B 2n ; a third emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n+1 and B 2n+1 to supply through a third emitter follower an exclusive logical sum A 5n+1 ⊕B 2n+1 ; the outputs of this third logic and the second logic being an emitter dotting which constitutes an AND gate for outputting a logic result (A 2n+1 ⊕B 2n+1 )·(A 2n ⊕B 2n ), a fourth emitter-coupled transistor logic of cascaded double-stage arrangement receiving the inputs A 2n+1 and B 2n+1 to produce a logical product A 2n+1 ·B 2n+1 , which is in turn connected to a fourth emitter follower coupled with a fifth emitter follower which receives the outputs of the second and third emitter-coupled logics so that the logical result A 2n+1 ·B 2n+1 +(A 2n+1 ⊕B 2n+1 )A 2n ·B 2n , can be obtained, and wherein the second circuit means including a plurality of AND-OR gate circuits of the collector-dot type, each of which includes a plurality of AND gates receiving the corresponding output of the first circuit means and an OR gate receiving the outputs of the AND gates, each of the AND gate circuits being composed to an emitter-coupled logic gate and the OR gate being constituted of a collector dotting having a transistor whose base is connected commonly to the collectors of the output transistors of all the AND gates.

Claim 7

An adder circuit for connection to a source of input signals and a source of external carry signals comprising: a plurality of adder circuits each for receiving from said source of input signals first and second binary signals of (M+1) bit length, each corresponding to a certain bit portion of the addend and augend and for producing the result of the addition of said first and second binary signals for each bit portion and a carry generate signal G i and a carry propagate signal P i ; and a carry look-ahead circuit coupled to said adder circuits; each of said adder circuits comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means connected to receive the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals in accordance with the following logical formula: G.sub.2n+1 =A.sub.2n+1 B.sub.2n+1 +(A.sub.2n+1 ⊕B.sub.2n+1)·A.sub.2n B.sub.2n P.sub.2n+1 =(A.sub.2n+1 ⊕B.sub.2n+1)·(A.sub.2n ⊕B.sub.2n) X.sub.2n+1 =A.sub.2n+1 ⊕B.sub.2n+1 X.sub.2n =A.sub.2n ⊕B.sub.2n Y.sub.2n =A.sub.2n ·B.sub.2n Wherein 2n=0, 2, 4, . . . , (M-1) and 2n+1=1, 3, . . . , M; and (b) said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula: ##EQU5## wherein C 0 =C IN =G -1 and C 1 =Y 0 +X 0 +X 0 C IN ; and (c) said third circuit means includes an Exclusive-OR circuit which receives one corresponding output X i from said first circuit means and the internal carry signal C i from a corresponding unit of said second circuit means so as to produce the sum signal S i for the addition of said first and second binary signals for the i th bit position thereof, said sum signal S i being expressed by the following logical formula: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 8

An adder circuit for connection to a source of input signals and a source of external carry signals comprising: a plurality of adder circuits each for receiving from said source of input signals first and second binary signals of (M+1) bit length, each corresponding to a certain bit portion of the addend and augend and for producing the result of the addition of said first and second binary signals for each bit portion and a carry generate signal G i and a carry propagate signal P i ; and a carry look-ahead circuit coupled to said adder circuits; each of said adder circuits comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means connected to receive the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals in accordance with the following logical formula: G.sub.2n+1 =A.sub.2n+1 B.sub.2n+1 +(A.sub.2n+1 ⊕B.sub.2n+1)·A.sub.2n B.sub.2n P.sub.2n+1 =(A.sub.2n+1 ⊕B.sub.2n+1)·(A.sub.2n ⊕B.sub.2n) X.sub.2n+1 =A.sub.2n+1 ⊕B.sub.2n+1 X.sub.2n =A.sub.2n ⊕B.sub.2n Y.sub.2n =A.sub.2n ·B.sub.2n Wherein 2n=0, 2, 4, . . . , (M-1) and 2n+1=1, 3, . . . , M; and (b) said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula: ##EQU5## wherein C 0 =C IN =G -1 and C 1 =Y 0 +X 0 +X 0 C IN ; and (c) said third circuit means includes an Exclusive-OR circuit which receives one corresponding output X i from said first circuit means and the internal carry signal C i from a corresponding unit of said second circuit means so as to produce the sum signal S i for the addition of said first and second binary signals for the i th bit position thereof, said sum signal S i being expressed by the following logical formula: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 9

An adder as claimed in claim 6, wherein said second circuit means produce a carry generate signal G and a carry propagate signal P of the following formula. G=G.sub.2n+1 +P.sub.2n+1 G.sub.2n-1 +P.sub.2n+1 P.sub.2n-1 G.sub.2n-3 + . . . +P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.5 P.sub.3 G.sub.1 P=P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.3 P.sub.1.

Claim 10

An adder as claimed in claim 7, wherein said carry lookahead circuit receives the carry generate signal G j-1 and the carry propagate signal P j-1 from each of said adder circuits and outputs a carry signal C j to the j-th adder circuit.

Claim 11

An adder as claimed in claim 8, wherein said carry signal C j is expressed by the following logical formula: C.sub.j =G.sub.j-i +P.sub.j-1 C.sub.j-1 wherein C 0 =C 1N .

Claim 12

An adder as claimed in claim 7, wherein said carry lookahead circuit produces a carry generate signal G total and a carry propagate signal P total for all of the inputted binary signals to said adder by the following logical formula: G.sub.total =G.sub.j +P.sub.j G.sub.j-1 + . . . +P.sub.j P.sub.j-1 . . . P.sub.2 P.sub.1 G.sub.0 P.sub.total =P.sub.j P.sub.j-1 P.sub.j-2 . . . P.sub.1 P.sub.0.

Claim 13

An adder as claimed in claim 6, wherein said first circuit means includes a plurality of arithmetic and logic arrays, each of which includes a current mode switching type transistor logic circuit having four switching type transistor logic circuits having four inputs for receiving the input bit signals A 2n+1 , A 2n , B 2n+1 , B 2n and five outputs for outputting the X 2n , X 2n+1 , Y 2n , G 2n+1 and P 2n+1 , the current mode switching type transistor logic circuit including: a first emitter-coupled transistor logic receiving the inputs A 2n and B 2n to provide through a first emitter follower a logical product A 2n ·B 2n ; a second emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n and B 2n to output through a second emitter follower an exclusive logic sum A 2n ⊕B 2n ; a third emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n+1 and B 2n+1 to supply through a third emitter follower an exclusive logical sum A 5n+1 ⊕B 2n+1 ; the outputs of this third logic and the second logic being an emitter dotting which constitutes an AND gate for outputting a logic result (A 2n+1 ⊕B 2n+1 )·(A 2n ⊕B 2n ), a fourth emitter-coupled transistor logic of cascaded double-stage arrangement receiving the inputs A 2n+1 and B 2n+1 to produce a logical product A 2n+1 ·B 2n+1 , which is in turn connected to a fourth emitter follower coupled with a fifth emitter follower which receives the outputs of the second and third emitter-coupled logics so that the logical result A 2n+1 ·B 2n+1 +(A 2n+1 ⊕B 2n+1 )A 2n ·B 2n , can be obtained, and wherein the second circuit means including a plurality of AND-OR gate circuits of the collector-dot type, each of which includes a plurality of AND gates receiving the corresponding output of the first circuit means and an OR gate receiving the outputs of the AND gates, each of the AND gate circuits being composed to an emitter-coupled logic gate and the OR gate being constituted of a collector dotting having a transistor whose base is connected commonly to the collectors of the output transistors of all the AND gates.

Claim 14

An adder circuit for connection to a source of input signals and a source of external carry signals comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means connected to receive the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n of the following logical formula: G.sub.2n+1 =A.sub.2n+1 B.sub.2n+1 +(A.sub.2n+1 ⊕B.sub.2n+1)·A.sub.2n B.sub.2n P.sub.2n+1 =(A.sub.2n+1 ⊕B.sub.2n+1)·(A.sub.2n ⊕B.sub.2n) X.sub.2n+1 =A.sub.2n+1 ⊕B.sub.2n+1 X.sub.2n =A.sub.2n ⊕B.sub.2n Y.sub.2n =A.sub.2n ·B.sub.2n Wherein 2n=0, 2, 4, . . . , (M-1) and 2n+1=1, 3, . . . , M; and (b) said third circuit means includes an Exclusive-OR circuit which receives one corresponding output X i from said first circuit means and the internal carry signal C i from a corresponding unit of said second circuit means so as to produce the sum signal S i for the addition of said first and second binary signals for the i th bit position thereof, said sum signal S i being expressed by the following logical formula: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 15

An adder circuit for connection to a source of input signals and a source of external carry signals comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means connected to receive the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n of the following logical formula: G.sub.2n+1 =A.sub.2n+1 B.sub.2n+1 +(A.sub.2n+1 ⊕B.sub.2n+1)·A.sub.2n B.sub.2n P.sub.2n+1 =(A.sub.2n+1 ⊕B.sub.2n+1)·(A.sub.2n ⊕B.sub.2n) X.sub.2n+1 =A.sub.2n+1 ⊕B.sub.2n+1 X.sub.2n =A.sub.2n ⊕B.sub.2n Y.sub.2n =A.sub.2n ·B.sub.2n Wherein 2n=0, 2, 4, . . . , (M-1) and 2n+1=1, 3, . . . , M; and (b) said third circuit means includes an Exclusive-OR circuit which receives one corresponding output X i from said first circuit means and the internal carry signal C i from a corresponding unit of said second circuit means so as to produce the sum signal S i for the addition of said first and second binary signals for the i th bit position thereof, said sum signal S i being expressed by the following logical formula: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 16

An adder circuit as claimed in claim 12, wherein said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula. ##EQU6## wherein C 0 =C 1N =G -1 and C 1 =Y 0 +X 0 C 1N .

Claim 17

An adder circuit as claimed in claim 13, wherein the second circuit means produce a carry generate signal G and a carry propagate signal P of the following formula. G=G.sub.2n+1 +P.sub.2n+1 G.sub.2n-1 +P.sub.2n+1 P.sub.2n-1 G.sub.2n-3 + . . . +P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.5 P.sub.3 G.sub.1 P=P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.3 P.sub.1.

Claim 18

An adder circuit as claimed in claim 13, wherein each of said arithmetic and logical circuits includes AND gates and OR gates which are constituted of current mode transistor switching circuits and which assembled to receive input signals A 2n+1 , A 2n , B 2n+1 and B 2n so as to generate five outputs G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n .

Claim 19

An adder circuit as claimed in claim 13, wherein said first circuit means includes a plurality of arithmetic and logic arrays, each of which includes a current mode switching type transistor logic circuit having four switching type transistor logic circuits having four inputs for receiving the input bit signals A 2n+1 , A 2n , B 2n+1 , B 2n and five outputs for outputting the X 2n , X 2n+1 , Y 2n , G 2n+1 and P 2n+1 , the current mode switching type transistor logic circuit including: a first emitter-coupled transistor logic receiving the inputs A 2n and B 2n to provide through a first emitter follower a logical product A 2n ·B 2n ; a second emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n and B 2n to output through a second emitter follower an exclusive logic sum A 2n ⊕B 2n ; a third emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n+1 and B 2n+1 to supply through a third emitter follower an exclusive logical sum A 2n+1 ⊕B 2n+1 ; the outputs of this third logic and the second logic being an emitter dotting which constitutes an AND gate for outputting a logic result (A 2n+1 ⊕B 2n+1 )·(A 2n ⊕B 2n ), a fourth emitter-coupled transistor logic of cascaded double-stage arrangement receiving the inputs A 2n+1 and B 2n+1 to produce a logical product A 2n+1 ·B 2n+1 , which is in turn connected to a fourth emitter follower coupled with a fifth emitter follower which receives the outputs of the second and third emitter-coupled logics so that the logical result A 2n+1 ·B 2n+1 +(A 2n+1 ⊕B 2n+1 ) A 2n ·B 2n , can be obtained, and wherein the second circuit means including a plurality of AND-OR gate circuits of the collector-dot type, each of which includes a plurality of AND gates receiving the corresponding output of the first circuit means and an OR gate receiving the outputs of the AND gates, each of the AND gate circuits being composed to an emitter-coupled logic gate and the OR gate being constituted of a collector dotting having a transistor whose base is connected commonly to the collectors of the output transistors of all the AND gates.

Claim 20

An adder for connection to a source of input signals and a source of external carry signals which comprises: a plurality of adder circuits each for receiving from said source of input signals first and second binary signals of (M+1) bit length each corresponding to a certain bit portion of the addend and augend and for producing the result of the addition of said first and second binary signals for each bit portion and a carry generate signal G i and a carry propagate signal P i ; and, a carry look-ahead circuit coupled to said adder circuits; each of said adder circuits comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means receiving the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n of the following logical formula; (b) said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula: ##EQU7## wherein C O =C IN =G -1 and C 1 =Y O +X O C IN ; and (c) said third circuit means produce the sum signal S i for the addition of said first and second binary signals for the i bit position thereof, said sum signal S i being expressed as follows: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 21

An adder for connection to a source of input signals and a source of external carry signals which comprises: a plurality of adder circuits each for receiving from said source of input signals first and second binary signals of (M+1) bit length each corresponding to a certain bit portion of the addend and augend and for producing the result of the addition of said first and second binary signals for each bit portion and a carry generate signal G i and a carry propagate signal P i ; and, a carry look-ahead circuit coupled to said adder circuits; each of said adder circuits comprising: first circuit means connected to receive first and second binary input signals A and B from said source of input signals, each of said signals corresponding to a certain bit length (M+1) of binary data, for producing parallel output signals; second circuit means receiving the output signals from said first circuit means and an external carry signal from the source of external carry signals for producing internal carry signals; third circuit means coupled to receive the parallel output signals from said first circuit means and the internal carry signals from said second circuit means for producing the result of the addition of said first and second binary input signals taking account of said external carry signal for each bit position thereof; and said adder circuit being characterized in that (a) said first circuit means comprises a plurality of arithmetic and logical circuits each receiving two pairs of the input bit signals (A 2n+1 , A 2n , B 2n+1 , B 2n ) which correspond to the contents of the two adjacent bits of said input binary signals and producing output signals G 2n+1 , P 2n+1 , X 2n+1 , X 2n and Y 2n of the following logical formula; (b) said second circuit means produce carry signal C 2n or C 2n+1 for each bit position of said first and second binary signals, said signals C 2n and C 2n+1 being expressed by the following logical formula: ##EQU7## wherein C O =C IN =G -1 and C 1 =Y O +X O C IN ; and (c) said third circuit means produce the sum signal S i for the addition of said first and second binary signals for the i bit position thereof, said sum signal S i being expressed as follows: S.sub.i =X.sub.i ⊕C.sub.i.

Claim 22

An adder as claimed in claim 17, wherein the second circuit means produce a carry generate signal G and a carry propagate signal P of the following logical formula: G=G.sub.2n+1 +P.sub.2n+1 G.sub.2n-1 +P.sub.2n+1 P.sub.2n-1 G.sub.2n-3 + . . . +P.sub.2n+1 P.sub.2n-1 P.sub.2n-3 . . . P.sub.5 P.sub.3 G.sub.1 P=P.sub.2n+1 P.sub.2n-1 P.sub.2n-3. . . P.sub.3 P.sub.1.

Claim 23

An adder as claimed in claim 18, wherein said carry lookahead circuit receives the carry generate signal G j and the carry propagate signal P j from each of said adder circuits and outputs a carry signal C j to the j-th adder circuit.

Claim 24

An adder as claimed in claim 19, wherein said carry signal C j is expressed by the following logical formula: C.sub.j =G.sub.j-1 +P.sub.j-1 C.sub.j-1 But, C 0 =C 1N .

Claim 25

An adder as claimed in claim 18, wherein said carry lookahead circuit produces a carry generate signal G total and a carry propagate signal P total for all of the inputted binary signals to said adder by the following logical formula: G.sub.total =G.sub.j +P.sub.j G.sub.j-1 + . . . +P.sub.j P.sub.j-1 . . . P.sub.2 P.sub.1 G.sub.0 P.sub.total =P.sub.j P.sub.j-1 P.sub.j-2 . . . P.sub.1 P.sub.0.

Claim 26

An adder as claimed in claim 17, wherein said first circuit means includes a plurality of airthmetic and logic arrys, each of which includes a current mode switching type transistor logic circuit having four switching type transistor logic circuits having four inputs for receiving the input bit signals A 2n+1 , A 2n , B 2n+1 , B 2n and five outputs for outputting the X 2n , X 2n+1 , Y 2n , G 2n+1 and P 2n+1 , the current mode switching type transistor logic circuit including: a first emitter-coupled transistor logic receiving the inputs A 2n and B 2n to provide through a first emitter follower a logical product A 2n ·B 2n ; a second emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n and B 2n to output through a second emitter follower an exclusive logic sum A 2n ⊕B 2n ; a third emitter-coupled transistor logic of cascaded double-stage construction receiving the inputs A 2n+1 and B 2n+1 to supply through a third emitter follower an exclusive logical sum A 2n+1 ⊕B 2n+1 ; the outputs of this third logic and the second logic being an emitter dotting which constitutes an AND gate for outputting a logic result (A 2n+1 ⊕B 2n+1 )·(A 2n ⊕B 2n ), a fourth emitter-coupled transistor logic of cascaded double-stage arrangement receiving the inputs A 2n+1 and B 2n+1 to produce a logical product A 2n+1 ·B 2n+1 , which is in turn connected to a fourth emitter follower coupled with a fifth emitter follower which receives the outputs of the second and third emitter-coupled logics so that the logical result A 2n+1 ·B 2n+1 +(A 2n+1 ⊕B 2n+1 ), A 2n ·B 2n , can be obtained, and wherein the second circuit means including a plurality of AND-OR gate circuits of the collector-dot type, each of which includes a plurality of AND gates receiving the corresponding output of the first circuit means and an OR gate receiving the outputs of the AND gates, each of the AND gate circuits being composed to an emitter-coupled logic gate and the OR gate being constituted of a collector dotting having a transistor whose base is connected commonly to the collectors of the output transistors of all the AND gates.