US4763330A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Syndrome calculating apparatus
Assignee: Kyocera Mita Industrial Co Ltd
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Filing: 1987-05-01
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Granted: 1988-08-09
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Expires: 2007-05-01
Abstract
Abstract Syndrome calculating apparatus in which a operation of the multiplication of each of the unit codes of a received code by power of the root α of the primitive polynomial in the Galois field is carried out first, a series of operations of the addition of the result by power of the root α to the next unit code and the multiplication of the result thus added by power of the root α are repeatedly carried out secondly so as to finally obtain syndromes, by a plurality of flip-flops disposed in parallel to one another, a pair of XOR gates disposed in parallel to each other for each of the flip-flops and a pair of AND gates for each of the flip-flops for selectively supplying the output data of the XOR gates to the flip-flops.
Inventors
- 👤 Hiroshi Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:06
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
179 words
Syndrome calculating apparatus to which received codes are successively supplied to obtain syndromes, comprising: first addition means for respectively supplying the bits of each of unit codes constituting a received code, to a plurality of latch means; second addition means for supplying, to at least one of said plurality of latch means, the output bit of at least one of said plurality of latch means; gate means for supplying the signals of said first and second addition means to said plurality of latch means, respectively; and gate control means for selectively opening said gate means; the output bits of said plurality of latch means being supplied to said first addition means connected to said plurality of latch means; the output bit of said at least one of said plurality of latch means being supplied to said second addition means connected to said at least one of said plurality of latch means so as to produce the same result as that obtained by the operation of multiplication of power of the root of the primitive polynomial in the Galois field.
Claim 2
Dependent Claim
179 words
Syndrome calculating apparatus to which received codes are successively supplied to obtain syndromes, comprising: first addition means for respectively supplying the bits of each of unit codes constituting a received code, to a plurality of latch means; second addition means for supplying, to at least one of said plurality of latch means, the output bit of at least one of said plurality of latch means; gate means for supplying the signals of said first and second addition means to said plurality of latch means, respectively; and gate control means for selectively opening said gate means; the output bits of said plurality of latch means being supplied to said first addition means connected to said plurality of latch means; the output bit of said at least one of said plurality of latch means being supplied to said second addition means connected to said at least one of said plurality of latch means so as to produce the same result as that obtained by the operation of multiplication of power of the root of the primitive polynomial in the Galois field.
Claim 3
Dependent Claim
18 words
Syndrome calculating apparatus as set forth in claim 1, wherein the Galois field is GF (2 m ).
Claim 4
Dependent Claim
295 words
Syndrome calculating apparatus to which received codes are successively supplied to obtain syndromes, comprising: a pair of calculating units to which unit codes in the odd place and unit codes in the even place are respectively entered successively; third addition means for adding the output bits of one of the pair of calculating units to which unit codes in the even place are successively entered, to one another so that such addition corresponds to the operation of multiplication of power of the root; and fourth addition means for adding the output bits of the other of said pair of calculating units to which unit codes in the odd place are successively entered, to the output bits of said third addition means in a correlative manner; and each calculating unit further comprises: first addition means for respectively supplying the bits of each of unit codes constituting a received code to a plurality of latch means; second addition means for supplying, to at least one of said plurality of latch means, the output bit of at least one of said plurality of latch means; gate means for supplying the signals of the first and second addition means to said plurality of latch means, respectively; gate control means for selectively opening said gate means; the output bits of said plurality of latch means being supplied to the first addition means connected to said plurality of latch means; the output bit of said at least one of said plurality of latch means being supplied to the second addition means connected to said at least one of said plurality of latch means so as to produce the same result as that obtained by the operation of multiplication of power of the root of the primitive polynomial in the Galois field.
Claim 5
Dependent Claim
295 words
Syndrome calculating apparatus to which received codes are successively supplied to obtain syndromes, comprising: a pair of calculating units to which unit codes in the odd place and unit codes in the even place are respectively entered successively; third addition means for adding the output bits of one of the pair of calculating units to which unit codes in the even place are successively entered, to one another so that such addition corresponds to the operation of multiplication of power of the root; and fourth addition means for adding the output bits of the other of said pair of calculating units to which unit codes in the odd place are successively entered, to the output bits of said third addition means in a correlative manner; and each calculating unit further comprises: first addition means for respectively supplying the bits of each of unit codes constituting a received code to a plurality of latch means; second addition means for supplying, to at least one of said plurality of latch means, the output bit of at least one of said plurality of latch means; gate means for supplying the signals of the first and second addition means to said plurality of latch means, respectively; gate control means for selectively opening said gate means; the output bits of said plurality of latch means being supplied to the first addition means connected to said plurality of latch means; the output bit of said at least one of said plurality of latch means being supplied to the second addition means connected to said at least one of said plurality of latch means so as to produce the same result as that obtained by the operation of multiplication of power of the root of the primitive polynomial in the Galois field.
Claim 6
Dependent Claim
18 words
Syndrome calculating apparatus as set forth in claim 3, wherein the Galois field is GF (2 m ).
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |