US4763303A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write-drive data controller
Assignee: NXP USA Inc
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Filing: 1986-02-24
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Granted: 1988-08-09
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Expires: 2006-02-24
Abstract
Abstract A write drive data control circuit for controlling the transmission of data to a memory array includes data input means for receiving complimentary data signals which are then transmitted to output circuits. The valid data is latched and the input circuits disabled. The output circuits remain enabled so as to pass the latched data to the memory array. After a predetermined period of time, the output circuits are disabled. In this manner, both the data set up time and data hold time may be independently optimized.
Inventors
- 👤 Stephen T. Flannagan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C7/1087
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
208 words
A write drive data control circuit for controlling the transmission of data to a memory array, comprising: data input means for receiving at at least one input thereof a serial data stream of alternating valid and invalid data, and having at least one output; control means coupled to said data input means for receiving a first control signal capable of assuming at least first and second stable states, said control means for enabling the passage of valid data from said at least one input to said at least one output when said first control signal is in said first state, and for disabling said data input means when said first control signal is in said second state; latching means coupled to said at least one output for latching the data appearing thereon when said first control signal changes from said first state to said second state; and data output means coupled to said latching means and to said at least one output for providing a data signal to said memory array from (i) said at least one output when said first control signal is in said first state, and (ii) from said latching means for a predetermined period of time after said data input means has been disabled.
Claim 2
Dependent Claim
208 words
A write drive data control circuit for controlling the transmission of data to a memory array, comprising: data input means for receiving at at least one input thereof a serial data stream of alternating valid and invalid data, and having at least one output; control means coupled to said data input means for receiving a first control signal capable of assuming at least first and second stable states, said control means for enabling the passage of valid data from said at least one input to said at least one output when said first control signal is in said first state, and for disabling said data input means when said first control signal is in said second state; latching means coupled to said at least one output for latching the data appearing thereon when said first control signal changes from said first state to said second state; and data output means coupled to said latching means and to said at least one output for providing a data signal to said memory array from (i) said at least one output when said first control signal is in said first state, and (ii) from said latching means for a predetermined period of time after said data input means has been disabled.
Claim 3
Dependent Claim
22 words
A circuit according to claim 1 further comprising disabling means for disabling said data output means after said predetermined period of time.
Claim 4
Dependent Claim
48 words
A circuit according to claim 2 wherein said data input means comprises: a first input circuit having a first input for receiving data thereon and having a first output; and a second input circuit having a second input for receiving complementary data thereon, and having a second output.
Claim 5
Dependent Claim
39 words
A circuit according to claim 3 wherein said control means comprises switching means coupled in series with each of said first and second data input circuits, the series combination being coupled between first and second sources of supply voltage.
Claim 6
Dependent Claim
29 words
A circuit according to claim 4 wherein said latching means comprises: a first latch circuit coupled to said first output; and a second latch coupled to said second output.
Claim 7
Dependent Claim
62 words
A circuit according to claim 5 wherein said data output means comprises: a first output circuit coupled to said first output and to said first latch circuit for providing a data output to said memory array; and a second output circuit coupled to said second output and to said second latch circuit for providing a complementary data output to said memory array.
Claim 8
Dependent Claim
65 words
A circuit according to claim 6 further comprising: at least a first switch coupled in series with said first latch between said first and second sources of supply voltage and controlled by said first control signal; and at least a second switch coupled in series with said second latch between said first and second sources of supply voltage and controlled by said first control signal.
Claim 9
Independent Claim
148 words
A method for controlling the writing of valid data into a memory array, comprising: receiving a serial data stream of alternately valid and invalid data at a data input circuit having at least one input and at least one output; receiving a first control signal capable of assuming at least first and second stable states; enabling the passage of valid data to said at least one output when said first control signal is in said first state; disabling said data input circuit when said first control signal is in said second state; latching said valid data in a latching circuit; and providing from an output circuit a data signal to said memory array (i) from said at least one output when said first control signal is in said first state and (ii) from said latching means for a predetermined period of time after disabling said data input circuit.
Claim 10
Independent Claim
148 words
A method for controlling the writing of valid data into a memory array, comprising: receiving a serial data stream of alternately valid and invalid data at a data input circuit having at least one input and at least one output; receiving a first control signal capable of assuming at least first and second stable states; enabling the passage of valid data to said at least one output when said first control signal is in said first state; disabling said data input circuit when said first control signal is in said second state; latching said valid data in a latching circuit; and providing from an output circuit a data signal to said memory array (i) from said at least one output when said first control signal is in said first state and (ii) from said latching means for a predetermined period of time after disabling said data input circuit.
Claim 11
Dependent Claim
18 words
A method according to claim 8 further comprising disabling said output circuit after said predetermined period of time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |