US4763251A
Expired / Lapsed
US
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Merge and copy bit block transfer implementation
Assignee: International Business Machines Corp
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Filing: 1986-01-17
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Granted: 1988-08-09
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Expires: 2006-01-17
Abstract
Abstract A memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.
Inventors
- 👤 Arthur A. Kauffman, Jr.
- 👤 John S. Muhich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:59
CPC Classifications
G; G06; G06T; G06T3/00; G06T3/60; G06T3/606; G06T1/00; G06T1/60
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
84 words
A memory circuit comprising: means for storing bit addressable binary data arranged in a plurality of dimensional directions; means for accessing a group of data in said storing means in at least two of said dimensional directions, said accessing means including means for selecting either incrementing or decrementing of a source address during the accessing of said data; and moving means for moving said group of data to a different dimensional location specified by a destination address while maintaining the data within the group.
Claim 2
Dependent Claim
84 words
A memory circuit comprising: means for storing bit addressable binary data arranged in a plurality of dimensional directions; means for accessing a group of data in said storing means in at least two of said dimensional directions, said accessing means including means for selecting either incrementing or decrementing of a source address during the accessing of said data; and moving means for moving said group of data to a different dimensional location specified by a destination address while maintaining the data within the group.
Claim 3
Dependent Claim
27 words
A memory circuit according to claim 1 wherein said selecting means includes means for selecting incrementing or decrementing said address in either of said two dimensional directions.
Claim 4
Dependent Claim
26 words
A memory circuit according to claim 2 wherein said selecting menas includes a latch to store a value selecting the incrementing or decrementing of said address.
Claim 5
Dependent Claim
41 words
A memory circuit according to claim 3 wherein said accessing means includes means for reading data in said storing means in a first dimensional direction and said moving means includes means for writing said data in a second different dimensional direction.
Claim 6
Dependent Claim
24 words
A memory circuit according to claim 4 wherein said accessing means includes means for accessing a variable number of bits in a single access.
Claim 7
Dependent Claim
38 words
A memory circuit according to claim 5 wherein said accessing means and said moving means are connected to means for performing logical operations upon data stored in different locations in said storing means and in different dimensional directions.
Claim 8
Dependent Claim
55 words
A memory circuit according to claim 6 wherein said logical operations means includes means for accessing a first group of data as source data, a second group of data as destination data, and performing a logical operation upon the source and destination data and storing the resulting data at the address of the destination data.
Claim 9
Dependent Claim
28 words
A memory circuit according to claim 1 wherein said accessing means includes means for incrementally or decrementally addressing said data in at least one of said dimensional directions.
Claim 10
Dependent Claim
82 words
A memory circuit comprising: means for storing bit addressable binary data arranged in a plurality of dimensional directions; means for accessing a group of data in said storing means at a specified source address in at least two of said dimensional directions; and moving means for moving said data to a different dimensional location while maintaining the data within the group, said moving means including means for selecting either incrementing or decrementing of a destination address during the accessing of said data.
Claim 11
Dependent Claim
82 words
A memory circuit comprising: means for storing bit addressable binary data arranged in a plurality of dimensional directions; means for accessing a group of data in said storing means at a specified source address in at least two of said dimensional directions; and moving means for moving said data to a different dimensional location while maintaining the data within the group, said moving means including means for selecting either incrementing or decrementing of a destination address during the accessing of said data.
Claim 12
Dependent Claim
27 words
A memory circuit according to claim 9 wherein said selecting means includes means for selecting incrementing or decrementing said address in either of said two dimensional directions.
Claim 13
Dependent Claim
26 words
A memory cirucit according to claim 10 wherein said selecting means includes a latch to store a value selecting the incrementing or decrementing of said address.
Claim 14
Dependent Claim
41 words
A memory circuit according to claim 11 wherein said accessing means includes means for reading data in said storing means in a first dimensional direction and said moving means includes means for writing said data in a second different dimensional direction.
Claim 15
Dependent Claim
24 words
A memory circuit according to claim 12 wherein said accessing means includes means for accessing a variable number of bits in a single access.
Claim 16
Dependent Claim
38 words
A memory circuit according to claim 13 wherein said accessing means and said moving means are connected to means for performing logical operations upon data stored in different locations in said storing means and in different dimensional directions.
Claim 17
Dependent Claim
55 words
A memory circuit according to claim 14 wherein said logical operations means includes means for accessing a first group of data as source data, a second group of data as destination data, and performing a logical operation upon the source and destination data and storing the resulting data at the address of the destination data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |