Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a semiconductor substraste having a surface and a first conductivity type; a plurality of cell groups which are formed on said substrate in such a manner that each group has a group area of a substantially square shape upon the substrate surface and includes four memory cells each having a switching transistor and a capacitor and a single semiconductor layer of a second conductivity type serving as a common drain region for all transistors included therein, said four memory cells being respectively positioned at four corners of the square-shaped cell area such that the area of the switching transistor and of the capacitor of one memory cell is symmetrical with the area of the switching transistor and of the capacitor of the diagonally associated memory cell; and parallel gate wiring lines which are electrically connected to gates of transistors included in said cell groups, said gate wiring lines being formed in first and second stacking wiring pattern layers which are provided over said substrate, and said square-shaped cell area being arranged on said substrate in such a manner as to be positioned aslant the extending direction of said gate wiring lines by substantially forty-five degrees.

Claim 3

The device according to claim 1, further comprising: a conductive layer provided above said substrate to serve as a common capacitor electrode for all capacitors of said memory device, said conductive layer also being made of polycrystalline semiconductor material.

Claim 4

The device according to claim 1, wherein said one cell group includes first to fourth memory cells which respectively have first to fourth transistors, said first to fourth transistors being connected to each other through said semiconductor layer as a common drain region formed at an intersection between first and second diagonal lines of said predetermined area and being arranged along the first and second diagonal lines in a cross-shape, said first and second cells opposing each other and said third and fourth cells opposing each other.

Claim 5

The device according to claim 3, wherein said first to fourth cells respectively have first to fourth capacitors, said first and second capacitors being respectively connected directly to said first and second transistors opposing each other along the first diagonal line and being arranged at first and second corners corresponding to the first diagonal line of said predetermined area, and said third and fourth capacitors being respectively connected directly to said third and fourth transistors opposing each other along the second diagonal line and being arranged at third and fourth corners corresponding to the second diagonal line of said predetermined area.

Claim 6

The device according to claim 4, further comprising: a first conductive layer which is provided above said substrate so as to be electrically insulated therefrom and which serves as a common capacitor electrode for all the capacitors of said memory device, said all the capacitors including said first to fourth capacitors included in said one cell group; a second conductive layer which is provided above said first conductive layer so as to be electrically insulated therefrom and which includes first gate electrode lines respectively connected to gates of said first and second transistors; and a third conductive layer which is provided above said second conductive layer so as to be electrically insulated therefrom and which includes second gate electrode lines respectively connected to gates of said third and fourth transistors.

Claim 7

The device according to claim 5, wherein said first to third conductive layers comprise a polycrystalline silicon material.

Claim 8

The device according to claim 5, further comprising: a fourth conductive layer which is provided above said third conductive layer so as to be insulated therefrom and which includes a drain electrode line connected to said common drain region of said first to fourth transistors.

Claim 9

A dynamic random access memory comprising: a semiconductive substrate of a first conductivity type having a surface; square-shaped cell units formed on said substrate in such a manner that each cell unit includes four memory cells which are respectively positioned at four corners thereof, and each of which has a switching transistor and a capactior positioned in a cell area whose planar shape is symmetrical with that of the diagonally associated memory cell, and a single semiconductor layer of a second conductivity type serving as a common drain region for all transistors included therein; and parallel conductive gate wiring lines which are electrically connected to gates of transistors included in said cell units, said gate wiring lines being formed in first and second stacking wiring pattern layers which are provided over said substrate, and each of said square-shaped cell units being positioned on said substrate aslant the extending direction of said gate wiring lines in such a manner that a first pair of memory cells consisting of two cells diagnonally associated therein are aligned in parallel with said gate wiring lines, and a second pair of memory cells consisting of the remaining two cells diagonally associated therein are aligned perpendicular to said wiring lines.

Claim 10

A dynamic random access memory comprising: a semiconductive substrate of a first conductivity type having a surface; square-shaped cell units formed on said substrate in such a manner that each cell unit includes four memory cells which are respectively positioned at four corners thereof, and each of which has a switching transistor and a capactior positioned in a cell area whose planar shape is symmetrical with that of the diagonally associated memory cell, and a single semiconductor layer of a second conductivity type serving as a common drain region for all transistors included therein; and parallel conductive gate wiring lines which are electrically connected to gates of transistors included in said cell units, said gate wiring lines being formed in first and second stacking wiring pattern layers which are provided over said substrate, and each of said square-shaped cell units being positioned on said substrate aslant the extending direction of said gate wiring lines in such a manner that a first pair of memory cells consisting of two cells diagnonally associated therein are aligned in parallel with said gate wiring lines, and a second pair of memory cells consisting of the remaining two cells diagonally associated therein are aligned perpendicular to said wiring lines.

Claim 11

The memory according to claim 8, wherein said gate wiring lines include: first gate wiring lines having branch line portions which extend in parallel with said second pair of memory cells in each of said square-shaped cell units, said branch line portions being connected to the transistors of said first pair of memory cells; and second gate wiring lines connected to the transistors of said second pair of memory cells.

Claim 12

The memory according to claim 9, wherein said first gate wiring lines are formed in said first wiring pattern layer, and wherein said second gate wiring lines are formed in said second wiring pattern layer which is stacked over said first wiring pattern layer.

Claim 13

The memory according to claim 10, wherein said square-shaped cell units are positioned on said substrate aslant the extending direction of said gate wiring lines by substantially forty-five degrees.