US4761753A
Expired / Lapsed
US
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Vector processing apparatus
Assignee: NEC Corp
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Filing: 1984-09-27
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Granted: 1988-08-02
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Expires: 2004-09-27
Abstract
Abstract A vector operation processing apparatus utilizes a plurality of vector registers in a pipeline computer architecture. The vector registers store ordered data elements which are processed in a pipelined vector operation unit in response to a vector instruction which designates selected ones of the vector registers. An input selection circuit is utilized for writing results of the operation performed by the pipelined vector operation unit into the vector registers which are designated by the vector instruction. A write control device is used for causing the writing operation to be performed exclusively on the plurality of vector registers in response to an indication by the vector instruction.
Inventors
- 👤 Hiroyuki Izumisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:58
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
109 words
A vector operation processing apparatus comprising: a plurality of vector registers for individually holding ordered data elements; a pipelined vector operation unit for processing said ordered data elements successively transmitted from a first pair of said vector registers which are designated by a vector instruction to produce intermediate operands; an input selection circuit for writing said intermediate operands into a second pair of said vector registers which are designated by said vector instruction; and a write control means which is responsive to a vector instruction which specifies an inner product operation for causing said writing operation to be performed alternately between said first and second pairs of vector registers.
Claim 2
Dependent Claim
109 words
A vector operation processing apparatus comprising: a plurality of vector registers for individually holding ordered data elements; a pipelined vector operation unit for processing said ordered data elements successively transmitted from a first pair of said vector registers which are designated by a vector instruction to produce intermediate operands; an input selection circuit for writing said intermediate operands into a second pair of said vector registers which are designated by said vector instruction; and a write control means which is responsive to a vector instruction which specifies an inner product operation for causing said writing operation to be performed alternately between said first and second pairs of vector registers.
Claim 3
Dependent Claim
27 words
A vector operation processing apparatus as recited in claim 1, wherein said vector operation unit comprises at least one of a vector adder and a vector multiplier.
Claim 4
Dependent Claim
94 words
A vector operation processing apparatus as recited in claim 1, wherein said vector operation unit comprises a vector adder and a vector multiplier and wherein said apparatus performs an inner product of an equation in the form of S=ΣA(j)*B(j), where J=1 to I in response to said vector instruction which specifies an inner product operation and said write control means causes intermediate results of multiplication and addition to be alternately stored between said designated first and second pairs of vector registers and wherein I is equal to the length of vectors A and B.
Claim 5
Dependent Claim
47 words
A vector operation processing apparatus as recited in claim 1, wherein said write control means comprises means for storing a vector length indication indicative of the number of times said write operation is performed exclusively and alternately on said first and second pairs of designated vector registers.
Claim 6
Dependent Claim
38 words
A vector operation processing apparatus as recited in claim 1, wherein said write control means includes at least one flip-flop and means for alternately setting and resetting said flip-flop to control write enable inputs of said designated registers.
Claim 7
Independent Claim
222 words
A method of processing data in a vector processing system comprising the steps of: (a) storing ordered data elements as operands in a plurality of vector registers; (b) in response to a vector instruction which specifies an inner product operation, successively transmitting said operands from a first pair of said plurality of vector registers to a vector processing unit in accordance with said vector instruction; (c) processing said operands in said vector processing unit in accordance with said vector instruction to produce intermediate results; (d) writing said intermediate results of said inner product operation produced in said processing step (c) exclusively and alternately in a designated second pair of said plurality of vector registers in accordance with said vector instruction; (e) successively transmitting said intermediate results from said second pair of said plurality of vector registers to said vector processing unit in accordance with said vector instructions; (f) processing said intermediate results in said vector processing unit in accordance with said vector instruction to produce additional intermediate results; (g) writing said additional intermediate results of said inner product operation produced in said processing step (f) exclusively and alternately into said first pair of said plurality of vector registers in accordance with said vector instruction; and (h) repeating steps (b)-(g) for said additional intermediate results as operands in accordance with said vector instructions.
Claim 8
Independent Claim
222 words
A method of processing data in a vector processing system comprising the steps of: (a) storing ordered data elements as operands in a plurality of vector registers; (b) in response to a vector instruction which specifies an inner product operation, successively transmitting said operands from a first pair of said plurality of vector registers to a vector processing unit in accordance with said vector instruction; (c) processing said operands in said vector processing unit in accordance with said vector instruction to produce intermediate results; (d) writing said intermediate results of said inner product operation produced in said processing step (c) exclusively and alternately in a designated second pair of said plurality of vector registers in accordance with said vector instruction; (e) successively transmitting said intermediate results from said second pair of said plurality of vector registers to said vector processing unit in accordance with said vector instructions; (f) processing said intermediate results in said vector processing unit in accordance with said vector instruction to produce additional intermediate results; (g) writing said additional intermediate results of said inner product operation produced in said processing step (f) exclusively and alternately into said first pair of said plurality of vector registers in accordance with said vector instruction; and (h) repeating steps (b)-(g) for said additional intermediate results as operands in accordance with said vector instructions.
Claim 9
Dependent Claim
215 words
A vector operation processing apparatus comprising: a first pair of vector registers for individually holding ordered data elements; a pipelined vector operation unit for processing said ordered data elements successively transmitted from said first pair of vector registers, said first pair of vector registers designated by a vector instruction, to produce intermediate operands; a second pair of vector registers; an input selection circuit for writing said intermediate operands into said second pair of vector registers, said second pair of vector registers designated by said vector instruction; a write control means responsive to a vector instruction which specifies an inner product operation for causing said writing operation to be performed exclusively and alternately on said designated second pair of vector registers; said vector operation unit further operative on said intermediate operands in said second pair of vector registers in response to said vector instruction for processing said intermediate operands to produce additional intermediate operands; said write control means being further responsive to said vector instruction which specifies said inner product operation to cause said additional intermediate operands from said vector operation unit to be written exclusively and alternately into said first pair of vector registers, such that intermediate results of an inner product operation are automatically written into said first and second pairs of vector registers.
Claim 10
Dependent Claim
215 words
A vector operation processing apparatus comprising: a first pair of vector registers for individually holding ordered data elements; a pipelined vector operation unit for processing said ordered data elements successively transmitted from said first pair of vector registers, said first pair of vector registers designated by a vector instruction, to produce intermediate operands; a second pair of vector registers; an input selection circuit for writing said intermediate operands into said second pair of vector registers, said second pair of vector registers designated by said vector instruction; a write control means responsive to a vector instruction which specifies an inner product operation for causing said writing operation to be performed exclusively and alternately on said designated second pair of vector registers; said vector operation unit further operative on said intermediate operands in said second pair of vector registers in response to said vector instruction for processing said intermediate operands to produce additional intermediate operands; said write control means being further responsive to said vector instruction which specifies said inner product operation to cause said additional intermediate operands from said vector operation unit to be written exclusively and alternately into said first pair of vector registers, such that intermediate results of an inner product operation are automatically written into said first and second pairs of vector registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |