US4761572A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor large scale integrated circuit with noise cut circuit
Assignee: Fujitsu Ltd
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Filing: 1987-03-13
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Granted: 1988-08-02
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Expires: 2007-03-13
Abstract
Abstract In a semiconductor large scale integrated circuit including a plurality of input terminals, sequential circuits and output buffer circuits, and further comprising a noise cut circuit, the semiconductor large scale integrated circuit comprises: a sense amplifier connected to an input terminal of the output buffer circuit for detecting a change of signal level at the input terminal and for generating an edge detection signal; a pluse generator connected to the sense amplifier for outputting a trigger pulse signal having a predetermined pulse width based on a plurality of the edge detection signals; and at least one tri-state circuit connected between the input terminal and the sequential circuit, and having a control terminal for receiving the trigger pulse signal for obtaining a high impedance state at an output line of the tri-state circuit during a predetermined period based on the trigger pulse signal input from the pulse generator.
Inventors
- 👤 Tetsu Tanizawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H03K19/00; H03K19/003; H03K19/00346; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
157 words
A semiconductor large scale integrated circuit including a pluraltiy of input terminals, sequential circuits and output buffer circuits connected to said sequential circuits, and further comprising a noise circuit comprising; a sense amplifier connected to an input terminal of said output buffer circuit for detecting a change of signal level at said input terminal and for generating an edge detection signal in response thereto; a pulse generator connected to said sense amplifier for outputting a trigger pulse signal having a predetermined pulse width in response to said edge detection signal from said sense amplifier; and at least one tri-state circuit connected between at least one of said input terminals and at least one of said sequential circuits, and having a control terminal for receiving said trigger pulse signal, for obtaining a high impedance state at an output line of said tri-state circuit during a predetermined period in response to said trigger signal input from said pulse generator.
Claim 2
Dependent Claim
157 words
A semiconductor large scale integrated circuit including a pluraltiy of input terminals, sequential circuits and output buffer circuits connected to said sequential circuits, and further comprising a noise circuit comprising; a sense amplifier connected to an input terminal of said output buffer circuit for detecting a change of signal level at said input terminal and for generating an edge detection signal in response thereto; a pulse generator connected to said sense amplifier for outputting a trigger pulse signal having a predetermined pulse width in response to said edge detection signal from said sense amplifier; and at least one tri-state circuit connected between at least one of said input terminals and at least one of said sequential circuits, and having a control terminal for receiving said trigger pulse signal, for obtaining a high impedance state at an output line of said tri-state circuit during a predetermined period in response to said trigger signal input from said pulse generator.
Claim 3
Dependent Claim
56 words
A semiconductor large scale integrated circuit as claimed in claim 1, wherein said sense amplifier comprises an exclusive-OR gate receiving an input signal from said input terminal for generating said edge detection signal having a predetermined pulse width wherein a delay circuit is provided for delaying said input signal to one input of said exclusive-OR gate.
Claim 4
Dependent Claim
102 words
A semiconductor large scale integrated circuit as claimed in claim 2, wherein said pulse generator comprises a plurality of inverter circuits, and said sense amplifier comprises a plurality of said exclusive-OR gates and said delay circuits each inverter circuit connected to a corresponding output of one of said exclusive-OR gates, a plurality of AND gates a corresponding connected to each output of said inverter circuits and all noncorresponding said exclusive-OR gates, an additional AND gate connected to each output of said exclusive-OR gates, and an OR gate connected to the outputs of all of said AND gates for outputting said trigger pulse.
Claim 5
Dependent Claim
78 words
A semiconductor large scale integrated circuit as claimed in claim 1, wherein said tri-state circuit comprises a P-channel transistor to which said trigger pulse signal is applied and an N-channel transistor to which an inverted trigger pulse signal is applied, said P-channel transistor and said N-channel transistor simultaneously being turned ON in response to said trigger pulse signal and said inverted trigger pulse signal, for obtaining a high impedance state at said output line during a predetermined period.
Claim 6
Dependent Claim
41 words
A semiconductor large scale integrated circuit as claimed in claim 1, wherein said high impedance state of said tri-state circuit during said predetermined period cuts noise caused by a fluctuation of a potential of a ground line at said input terminals.
Claim 7
Dependent Claim
51 words
A semiconductor large scale integrated circuit as claimed in claim 1, wherein said sequential circuit comprises a flip-flop circuit having a control signal input terminal for receiving a control signal and changing the internal state thereof, said tri-state circuit having said output line operatively connected to said control signal input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |