US4760554A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Staggered contacts in arrays of programmable memory cells
Assignee: Texas Instruments Inc
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Filing: 1986-08-15
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Granted: 1988-07-26
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Expires: 2006-08-15
Abstract
Abstract An array of programmable memory cells having spaced apart bit lines, spaced conducting word lines crossing over the bit lines and electrically conductive lead lines crossing over the word line which includes electrically conductive contacts between lead lines and corresponding bit lines. Each contact is located at an opposite side of a selected number of word lines to contacts between adjacent lead lines and associated bit lines so that when viewed in plan the contacts are staggered from one lead line to the next.
Inventors
- 👤 John F. Schreck
- 👤 Timmie M. Coffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 01:35
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
125 words
An array of electrical connections for programmable memory cells having spaced apart source/drain bit lines, spaced apart electrically conducting word lines crossing over the bit lines and spaced apart electrically conducting lead lines corresponding to and running parallel to said bit lines, said lead lines crossing over said word lines, said array having electrically conducting contact between each said lead line and each said corresponding bit line wherein each contact is located a selected number of word lines from the nearest adjacent contact between each said lead and bit line, comprising: said contacts between each said lead line and bitline positioned at points located substantially one-half of said selected number of word lines from the corresponding contacts of each adjacent lead line and bit line.
Claim 2
Dependent Claim
125 words
An array of electrical connections for programmable memory cells having spaced apart source/drain bit lines, spaced apart electrically conducting word lines crossing over the bit lines and spaced apart electrically conducting lead lines corresponding to and running parallel to said bit lines, said lead lines crossing over said word lines, said array having electrically conducting contact between each said lead line and each said corresponding bit line wherein each contact is located a selected number of word lines from the nearest adjacent contact between each said lead and bit line, comprising: said contacts between each said lead line and bitline positioned at points located substantially one-half of said selected number of word lines from the corresponding contacts of each adjacent lead line and bit line.
Claim 3
Dependent Claim
35 words
An array according to claim 1, wherein said word lines are doped polysilicon, said lead lines are metal and said bit lines are doped regions formed in a semiconductor substrate of a first conductivity type.
Claim 4
Dependent Claim
17 words
An array according to claim 1, wherein said memory cells are electrically programmable read only memory cells.
Claim 5
Dependent Claim
16 words
An array according to claim 2, wherein said doped regions are N + type conductivity regions.
Claim 6
Dependent Claim
13 words
An array according to claim 1, wherein said word lines are regularly spaced.
Claim 7
Dependent Claim
18 words
An array according to claim 1, wherein the number of word lines between each adjacent contact is 16.
References Cited (Backward Citations)
US4481609A
Cited
US4627028A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |