Patent US4760550A successfully refreshed from Google Patents.
US4760550A
Expired / Lapsed
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Saving cycles in floating point division
Assignee: AMADHL Corp A CORP OF DE
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Filing: 1986-09-11
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Granted: 1988-07-26
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Expires: 2006-09-11
Abstract
Abstract In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor have been normalized.
Inventors
- 👤 Solomon J. Katzman
- 👤 Stephen J. Rawlinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3832; G06F2207/3844; G06F2207/535; G06F2207/5352; G06F7/483; G06F7/487; G06F7/4873; G06F7/499; G06F7/49936
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
197 words
A method of dividing a pair of binary coded hexidecimal floating point numbers including a dividend N and a divisor D wherein said N includes an exponential part EXP(N) and a fractional part FRAC(N), said FRAC(N) including a most significant digit (N 0 ) and said D includes an exponential part EXP(D) and a fractional part FRAC(D), said FRAC(D) including a most significant digit (D 0 ), comprising in sequence the steps of: normalizing said FRAC(N) and said FRAC(D); comparing said N 0 and said D 0 ; transferring said FRAC(N) to a partial remainder register without shifting said FRAC(N) when said N 0 <D 0 ; shifting said FRAC(N) four bits to the right and transferring said shifted FRAC(N) to said partial remainder register when said N 0 ≧4×D 0 ; shifting said FRAC(N) two bits to the right and transferring said shifted FRAC(N) to said partial remainder register when said D 0 ≦N 0 <4×D 0 ; dividing the contents of said partial remainder register by said FRAC(D) in a predetermined number of machine cycles, each of said machine cycles producing a pair of quotient bits; and accumulating said quotient bits in an accumulating register.
Claim 2
Independent Claim
197 words
A method of dividing a pair of binary coded hexidecimal floating point numbers including a dividend N and a divisor D wherein said N includes an exponential part EXP(N) and a fractional part FRAC(N), said FRAC(N) including a most significant digit (N 0 ) and said D includes an exponential part EXP(D) and a fractional part FRAC(D), said FRAC(D) including a most significant digit (D 0 ), comprising in sequence the steps of: normalizing said FRAC(N) and said FRAC(D); comparing said N 0 and said D 0 ; transferring said FRAC(N) to a partial remainder register without shifting said FRAC(N) when said N 0 <D 0 ; shifting said FRAC(N) four bits to the right and transferring said shifted FRAC(N) to said partial remainder register when said N 0 ≧4×D 0 ; shifting said FRAC(N) two bits to the right and transferring said shifted FRAC(N) to said partial remainder register when said D 0 ≦N 0 <4×D 0 ; dividing the contents of said partial remainder register by said FRAC(D) in a predetermined number of machine cycles, each of said machine cycles producing a pair of quotient bits; and accumulating said quotient bits in an accumulating register.
Claim 3
Dependent Claim
89 words
A method according to claim 1 wherein said dividing and accumulating steps comprise the steps of: transferring a first and succeeding alternate pairs of said quotient bits in a Q-bits register during a first and succeeding alternate machine cycles; and transferring the contents of said Q-bits register and a second and succeeding alternate pairs of said quotient bits to said accumulating register during a second and succeeding alternate machine cycles, each of said second and succeeding alternate machine cycles following one of said first and succeeding alternate machine cycles.
Claim 4
Dependent Claim
58 words
A method according to claim 2 wherein said dividing and accumulating steps comprise the steps of transferring the contents of bit positions 4 to M+4 in said accumulating register to bit positions 0 to M in said accumulating register at the beginning of said second and succeeding alternate machine cycles, said M comprising a predetermined number of bits.
Claim 5
Dependent Claim
44 words
A method according to claim 2 wherein said dividing and accumulating steps comprise the steps of: storing the remainder of the subtraction EXP(N)-EXP(D) in an exponent result register EXP(R); and increasing the contents of said exponent register EXP(R) when N 0 ≧4×D 0 .
Claim 6
Dependent Claim
86 words
A method according to claim 2 wherein said dividing and accumulating steps comprise the step of: selectively increasing the number of machine cycles required for dividing said FRAC(N) by said FRAC(D) when D 0 ≦N 0 <4×D 0 and said first pair of quotient bits are 0; storing the remainder of the subtraction EXP(N)-EXP(D) in an exponent result register EXP(R); and increasing the contents of said exponent register EXP(R) when D 0 ≦N 0 <4×D 0 and said first pair of quotient bits are not 0.
Claim 7
Independent Claim
211 words
An apparatus for dividing a pair of binary coded hexidecimal floating point numbers including a dividend N and a divisor D wherein said N includes an exponential part EXP(N) and a fractional part FRAC(N), said FRAC(N) including a most significant digit (N 0 ) and said D includes an exponential part EXP(D) and a fractional part FRAC(D), said FRAC(D) including a most significant digit (D 0 ), comprising: a partial remainder register; an accumulating register; means for normalizing said FRAC(N) and said FRAC(D); means for comparing said N 0 and said D 0 ; means for transferring said FRAC(N) to said partial remainder register, including shifter means for shifting said FRAC(N), and means coupled to said comparing means for transferring said FRAC(D) without shift when said N 0 <D 0 , and providing said FRAC(D) transferred a shift of two bit to the right when said D 0 ≦N 0 <4×D 0 and a shift of four bit to the right of when said N 0 ≧4×D 0 ; means for dividing the contents of said partial remainder register by said FRAC(D) in a predetermined number of machine cycles, each of said machine cycles producing a pair of quotient bits; and means for accumulating said quotient bits to said accumulating register.
Claim 8
Independent Claim
211 words
An apparatus for dividing a pair of binary coded hexidecimal floating point numbers including a dividend N and a divisor D wherein said N includes an exponential part EXP(N) and a fractional part FRAC(N), said FRAC(N) including a most significant digit (N 0 ) and said D includes an exponential part EXP(D) and a fractional part FRAC(D), said FRAC(D) including a most significant digit (D 0 ), comprising: a partial remainder register; an accumulating register; means for normalizing said FRAC(N) and said FRAC(D); means for comparing said N 0 and said D 0 ; means for transferring said FRAC(N) to said partial remainder register, including shifter means for shifting said FRAC(N), and means coupled to said comparing means for transferring said FRAC(D) without shift when said N 0 <D 0 , and providing said FRAC(D) transferred a shift of two bit to the right when said D 0 ≦N 0 <4×D 0 and a shift of four bit to the right of when said N 0 ≧4×D 0 ; means for dividing the contents of said partial remainder register by said FRAC(D) in a predetermined number of machine cycles, each of said machine cycles producing a pair of quotient bits; and means for accumulating said quotient bits to said accumulating register.
Claim 9
Dependent Claim
95 words
An apparatus according to claim 6 comprising a Q-bits register and wherein said dividing and accumulating means comprise: means for transferring a first and succeeding alternate pairs of said quotient bits to said Q-bits register during a first and succeeding alternate machine cycles; and means for transferring the contents of said Q-bits register and a second and succeeding alternate pairs of said quotient bits to said accumulating register during a second and succeeding alternate machine cycles, each of said second and succeeding alternate machine cycles following one of said first and succeeding alternate machine cycles.
Claim 10
Dependent Claim
57 words
An apparatus according to claim 7 wherein said dividing and accumulating means comprise means for transferring the contents of bit positions 4 to M+4 in said accumulating register to bit positions 0 to M in said accumulating register at the beginning of said second and succeeding alternate machine cycles, said M comprising a predetermined number of bits.
Claim 11
Dependent Claim
52 words
An apparatus according to claim 7 comprising an exponent result register EXP(R) and wherein said dividing and accumulating means comprise: means for storing the remainder of the subtraction EXP(N)-EXP(D) in said exponent result register EXP(R); and means for increasing the contents of said exponent register EXP(R) when N 0 ≧4×D 0 .
Claim 12
Dependent Claim
96 words
An apparatus according to claim 7 comprising an exponent result register EXP(R) and wherein said dividing and accumulating means comprise: means for selectively increasing the number of machine cycles required for dividing said FRAC(N) by said FRAC(D) when D 0 ≦N 0 <4×D 0 and said first pair of quotient bits are 0; means for storing the remainder of the subtraction EXP(N)-EXP(D) in said exponent result register EXP(R); and means for increasing the contents of said exponent register EXP(R) when D 0 ≦N 0 <4×D 0 and said first pair of quotient bits are not 0.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |