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US4760524A
Expired / Lapsed
US
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Microcomputer having at least one input-output unit
Assignee: NEC Electronics Corp
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Filing: 1985-08-12
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Granted: 1988-07-26
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Expires: 2005-08-12
Abstract
Abstract A microcomputer includes a central processing unit and at least one input-output (peripheral) unit selected by an address on a single semiconductor chip. The microcomputer further has an address changing circuit for assigning an arbitrary address to the input-output unit, so that the input-output address can be accessed by a variable address.
Inventors
- 👤 Junichi Iwasaki
- 👤 Akira Kuwata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F13/00; G06F13/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
181 words
A microcomputer comprising a central processing unit executing a program, a plurality of input-output units, a plurality of selection lines respectively coupled to said input output units, a bus interconnecting said central processing unit and said input-output unit, said central processing unit generating address information designating one of said input-output units, a plurality of associative memory means respectively coupled to said selection lines, address data lines coupled in common to said plurality of associative memory means, means coupled to said plurality of associative memory means and to said address data lines for writing preset information into each of said plurality of associative memory means via said common address data lines, means coupled to said central processing unit and said address data lines for supplying said address information from said central processing unit to said plurality of associative memory means via said address data lines, and means for selecting the one of said selection lines that is coupled to the one of said associative memory means which stores the preset information coincident with said address information supplied from said central processing unit.
Claim 2
Dependent Claim
181 words
A microcomputer comprising a central processing unit executing a program, a plurality of input-output units, a plurality of selection lines respectively coupled to said input output units, a bus interconnecting said central processing unit and said input-output unit, said central processing unit generating address information designating one of said input-output units, a plurality of associative memory means respectively coupled to said selection lines, address data lines coupled in common to said plurality of associative memory means, means coupled to said plurality of associative memory means and to said address data lines for writing preset information into each of said plurality of associative memory means via said common address data lines, means coupled to said central processing unit and said address data lines for supplying said address information from said central processing unit to said plurality of associative memory means via said address data lines, and means for selecting the one of said selection lines that is coupled to the one of said associative memory means which stores the preset information coincident with said address information supplied from said central processing unit.
Claim 3
Dependent Claim
44 words
The microcomputer as claimed in claim 1, wherein said central processing unit, said input-output units, said selection lines, said bus, said plurality of associative memory means, said address data lines, said writing means, and said supplying means are integrated on a single semiconductor chip.
Claim 4
Dependent Claim
27 words
The microcomputer as claimed in claim 1, wherein said input-output units includes a DMA unit, an interruption control unit, a serial communication unit, and a timer/counter unit.
Claim 5
Dependent Claim
236 words
A microcomputer comprising a central processing unit, a plurality of input-output units each including a plurality of registers, a plurality of associative memory means, a data bus interconnecting said central processing unit and each of said input-output units, a first address bus interconnecting said central processing unit and each of said associative memory means, a second adress bus interconnecting said central processing unit and each of said input-output units, a plurality of selection lines each connected between each of said input-output units and each of said plurality of associative memory means, means coupled to said plurality of associative memory means for writing preset information into each of said plurality of associative memory means, said central processing unit producing a first address information selecting one of said input-output units and a second address information selecting one of said registers, means for transferring said first address information to said plurality of associative memory means via said first address bus, means for transferring said second address information to said plurality of input-output units via said second address bus, and means for selecting the one of said selection lines that is coupled to the associative memory means storing the preset information identical to said first address information, whereby the one of said input-output units connected to the selected selection line is selected and one of said registers included in the selected input-output unit is selected by said second address information.
Claim 6
Dependent Claim
236 words
A microcomputer comprising a central processing unit, a plurality of input-output units each including a plurality of registers, a plurality of associative memory means, a data bus interconnecting said central processing unit and each of said input-output units, a first address bus interconnecting said central processing unit and each of said associative memory means, a second adress bus interconnecting said central processing unit and each of said input-output units, a plurality of selection lines each connected between each of said input-output units and each of said plurality of associative memory means, means coupled to said plurality of associative memory means for writing preset information into each of said plurality of associative memory means, said central processing unit producing a first address information selecting one of said input-output units and a second address information selecting one of said registers, means for transferring said first address information to said plurality of associative memory means via said first address bus, means for transferring said second address information to said plurality of input-output units via said second address bus, and means for selecting the one of said selection lines that is coupled to the associative memory means storing the preset information identical to said first address information, whereby the one of said input-output units connected to the selected selection line is selected and one of said registers included in the selected input-output unit is selected by said second address information.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |