Patent US3786889A successfully refreshed from Google Patents.
Patent US4760449A successfully refreshed from Google Patents.
US4760449A
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Video signal processing apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1986-04-01
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Granted: 1988-07-26
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Expires: 2006-04-01
Abstract
Abstract A video signal processing apparatus incorporates a 1H or 2H delay circuit, wherein H is a horizontal synchronization period. The output of the delay circuit is fed back to the input thereof so as to average the noise, thus raising the signal S/N ratio. The feedback line includes a nonlinear processing circuit which has a small gain when the signal input has a low vertical correlation, whereby the signal S/N ratio is improved without causing the delay of the color signal in the vertical direction nor the deteriorated resolution of the luminance signal.
Inventors
- 👤 Tokikazu Matsumoto
- 👤 Yukio Nakagawa
- 👤 Masahiro Honjo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:39
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N9/00; H04N9/64; H04N9/646; H04N5/911
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
223 words
A video signal processing apparatus comprising: a delay circuit for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing circuit for receiving an output signal of said first operational circuit as a signal input thereto and for generating first and second output signals, said nonlinear processing circuit arranged such that said first output signal has a gain of K with respect to said signal input thereto that decreases with an increase of an absolute value of the level of said output signal from said first operational circuit and becomes zero when said absolute value exceeds a specified value, and said second output signal has a gain of 1/2(1+K) with respect to said signal input thereto; a second operational circuit for conducting an addition or subtraction operation between said first output signal of said nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; and a third operational circuit for conducting an addition or subtraction operation between said second output signal of said nonlinear processing circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 2
Dependent Claim
223 words
A video signal processing apparatus comprising: a delay circuit for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing circuit for receiving an output signal of said first operational circuit as a signal input thereto and for generating first and second output signals, said nonlinear processing circuit arranged such that said first output signal has a gain of K with respect to said signal input thereto that decreases with an increase of an absolute value of the level of said output signal from said first operational circuit and becomes zero when said absolute value exceeds a specified value, and said second output signal has a gain of 1/2(1+K) with respect to said signal input thereto; a second operational circuit for conducting an addition or subtraction operation between said first output signal of said nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; and a third operational circuit for conducting an addition or subtraction operation between said second output signal of said nonlinear processing circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 3
Dependent Claim
30 words
A video signal processing apparatus as claimed in claim 1, wherein said delay circuit delays said signal input thereto by 1H or 2H, wherein H is a horizontal synchronization period.
Claim 4
Dependent Claim
254 words
A video signal processing apparatus comprising: a delay circut for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a first nonlinear processing circuit for receiving an output signal of said first operational circuit as an input signal thereto and for generating an output signal, said first nonlinear processing circuit arranged such that said output signal has a gain of K with respect to said signal input thereto which decreases with an increase of an absolute value of the level of said output signal from said first opeational circuit and becomes zero when said absolute value exceeds a specified value; a second operational circuit for conducting an addition or subtraction operation between an output signal of said first nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; a second nonlinear processing circuit for receiving said output signal of said first operational circuit as an input signal thereto and for generating an output signal, said second nonlinear processing circuit arranged such that said output signal has a gain of 1/2(1+K) with respect to said signal input thereto; and a third operational circuit for conducting an addition or subtraction operation between said output signal of said second nonlinear processing circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 5
Dependent Claim
254 words
A video signal processing apparatus comprising: a delay circut for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or subtraction operation between an output signal of said delay circuit and an input video signal; a first nonlinear processing circuit for receiving an output signal of said first operational circuit as an input signal thereto and for generating an output signal, said first nonlinear processing circuit arranged such that said output signal has a gain of K with respect to said signal input thereto which decreases with an increase of an absolute value of the level of said output signal from said first opeational circuit and becomes zero when said absolute value exceeds a specified value; a second operational circuit for conducting an addition or subtraction operation between an output signal of said first nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; a second nonlinear processing circuit for receiving said output signal of said first operational circuit as an input signal thereto and for generating an output signal, said second nonlinear processing circuit arranged such that said output signal has a gain of 1/2(1+K) with respect to said signal input thereto; and a third operational circuit for conducting an addition or subtraction operation between said output signal of said second nonlinear processing circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 6
Dependent Claim
30 words
A video signal processing apparatus as claimed in claim 3, wherein said delay circuit delays said signal input thereto by 1H or 2H, wherein H is a horizontal synchronization period.
Claim 7
Dependent Claim
25 words
A video signal processing apparatus as claimed in claim 3, wherein said input video signal is a carrier chorminance signal modulated by a chrominance sub-carrier.
Claim 8
Dependent Claim
29 words
A video signal processing apparatus as claimed in claim 3, wherein said input video signal is a chrominance difference signal demodulated in the basic band or a luminance signal.
Claim 9
Dependent Claim
236 words
A video signal processing apparatus comprising: a delay circuit for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or substraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing ciruit for receiving an output signal of said first operational circuit as an input signal thereto and for generating an output signal, said nonlinear processing circuit arranged such that said output signal has a gain with respect to said signal input thereto which decreases with an increase of an absolute value of the level of said output signal from said first operational circuit and becomes zero when said absolute value exceeds a specified value; a second operational circuit for conducting an addition or subtraction operation between an output signal of said nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; an adder circuit for adding said output signal from said nonlinear processing circuit to said output signal from said first operational circuit; a coefficient circuit for multiplying an output signal of said adder circuit by a predetermined coefficient; and a third operational circuit for conducting an addition or subtraction operation between an output signal of said coefficient circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 10
Dependent Claim
236 words
A video signal processing apparatus comprising: a delay circuit for delaying a signal input thereto by a predetermined period of time; a first operational circuit for conducting an addition or substraction operation between an output signal of said delay circuit and an input video signal; a nonlinear processing ciruit for receiving an output signal of said first operational circuit as an input signal thereto and for generating an output signal, said nonlinear processing circuit arranged such that said output signal has a gain with respect to said signal input thereto which decreases with an increase of an absolute value of the level of said output signal from said first operational circuit and becomes zero when said absolute value exceeds a specified value; a second operational circuit for conducting an addition or subtraction operation between an output signal of said nonlinear processing circuit and said input video signal and for outputting an operation result as said signal input to said delay circuit; an adder circuit for adding said output signal from said nonlinear processing circuit to said output signal from said first operational circuit; a coefficient circuit for multiplying an output signal of said adder circuit by a predetermined coefficient; and a third operational circuit for conducting an addition or subtraction operation between an output signal of said coefficient circuit and said input video signal and for outputting, as an operation result, a noise reduced video signal.
Claim 11
Dependent Claim
30 words
A video signal processing apparatus as claimed in claim 7, wherein said delay circuit delays said signal input thereto by 1H or 2H, wherein H is a horizontal synchronization period.
Claim 12
Dependent Claim
20 words
A video signal processing apparatus as claimed in claim 7, wherein said predetermined coefficient of said coefficient circuit is 1/2.
Claim 13
Dependent Claim
25 words
A video signal processing apparatus as claimed in claim 7, wherein said input video signal is a carrier chrominance signal modulated by a chrominance sub-carrier.
Claim 14
Dependent Claim
29 words
A video signal processing apparatus as claimed in claim 7, wherein said input video signal is a chrominance difference signal demodulated in the basic band or a luminance signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |