Patent US4760291A successfully refreshed from Google Patents.
US4760291A
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US
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Synchronous bus type semiconductor circuit wherein two control signals share common terminal
Assignee: Mitsubishi Electric Corp
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Filing: 1987-05-27
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Granted: 1988-07-26
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Expires: 2007-05-27
Abstract
Abstract A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a "H" level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the "H" level or the "L" level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.
Inventors
- 👤 Toyokatsu Nakajima
- 👤 Tatsuo Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:46
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
165 words
A semiconductor IC device of an asynchronous bus type which is selected by a chip select signal, and which comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal line for transfer of a first and a second control signal each of which is not activated when the other is activated, wherein said first control signal is allocated to a first one of the "H" level and the "L" level of the external control signal, and said second control signal is activated when the external control line is at the second level which is the inverse of the first level for said first control signal, said semiconductor IC device further comprising an inhibit circuit for preventing said second control signal from being erroneously activated while said first control signal is to be activated, and when the first level of said external control signal begins after or terminates before said chip select signal.
Claim 2
Dependent Claim
165 words
A semiconductor IC device of an asynchronous bus type which is selected by a chip select signal, and which comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal line for transfer of a first and a second control signal each of which is not activated when the other is activated, wherein said first control signal is allocated to a first one of the "H" level and the "L" level of the external control signal, and said second control signal is activated when the external control line is at the second level which is the inverse of the first level for said first control signal, said semiconductor IC device further comprising an inhibit circuit for preventing said second control signal from being erroneously activated while said first control signal is to be activated, and when the first level of said external control signal begins after or terminates before said chip select signal.
Claim 3
Dependent Claim
33 words
A device according to claim 1, further comprising an AND gate for receiving the chip select signal and the external control signal, the output of said AND gate constituting said first control signal.
Claim 4
Dependent Claim
83 words
A device according to claim 2, wherein said inhibit circuit comprises a delay circuit receiving said external control signal and producing a delayed signal, and a NOR gate receiving the external control signal and the delayed signal and producing an inverse of a logical sum of the two input signals, and said device further comprises a second AND gate receiving the chip select signal and the output of the NOR gate, the output of the second AND gate constituting said second control signal.
Claim 5
Dependent Claim
79 words
A device according to claim 2, further comprising an inverter receiving the external control signal, and a second AND gate receiving the output of the inverter and the chip select signal, wherein said inhibit circuit comprises a delay circuit receiving the output of the second AND gate, and a third AND gate receiving the output of the delay circuit and the output of the second AND gate, the output of the third AND gate constituting said second control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |