Time switch with a dual memory structure-type control memory

Claim 2

A time switch with a dual memory structure-type control memory utilizing a time division time switch equipped with a speech memory unit into which digital signals to be interchanged are temporarily written and a control memory unit into which addresses to be accessed by said speech memory unit are written, wherein the time division switch comprises: a control memory unit having first and second memories and a memory controller, each memory having an address input, data input, data output and write enable signal input, the controller having an address output connected to the address inputs of both memories, a data output connected to the data inputs of both memories and a write enable signal output connected to the write enable signal inputs of both memories; said memories being set during hard and soft cycles so that when either one of the memories is set in a hard cycle which is a speech-control read-only mode, the other memory is set in a soft cycle, which is a speech-control data read-write mode under control from the memory controller; the soft cycle and hard cycle modes of said two memories being switched between each other in response to a mode switching signal.

Claim 3

A time switch with a dual memory structure-type control memory as claimed in claim 1, wherein the modes of said first and second memories are switched between each other immediately after the execution of control data writing into the first memory in the soft cycle, and the same control data is written into the second memory at the same memory address as that of the execution into said first memory.

Claim 4

A time switch with a dual memory structure-type control memory as claimed in claim 1, further comprising a path controller for synchronizing a speech control memory rewrite completion signal, supplied from a timing controller, with a frame pulse determining the timing of control data reading from said control memory, and using the output of said path controller as said mode switching signal.

Claim 5

A time switch with a dual memory structure-type control memory comprising; a control memory unit having a first memory in a hard cycle, which is a speech-control data read-only mode, and a second memory in a soft cycle, which is a mode for reading speech-control data out of, or writing them into, a path controller, and means for switching the modes of said first and second memories in response to a mode switching signal; a speech memory unit having first and second memory elements controlled by said control memory unit one memory element being set in the speech data write mode for writing frame-forming speech data for each time slot, the other memory element being set in the speech data read mode for reading out one frame of speech data for each time slot, and means for switching the modes of said speech memory elements in synchronization with the frame fromed speech data; and a timing controller for supplying as mode switching signal a control memory write completion signal supplied from a path controller, to said control memory unit in synchronization with the frame pulse.

Claim 6

A time switch with a dual memory structure-type control memory comprising; a control memory unit having a first memory in a hard cycle, which is a speech-control data read-only mode, and a second memory in a soft cycle, which is a mode for reading speech-control data out of, or writing them into, a path controller, and means for switching the modes of said first and second memories in response to a mode switching signal; a speech memory unit having first and second memory elements controlled by said control memory unit one memory element being set in the speech data write mode for writing frame-forming speech data for each time slot, the other memory element being set in the speech data read mode for reading out one frame of speech data for each time slot, and means for switching the modes of said speech memory elements in synchronization with the frame fromed speech data; and a timing controller for supplying as mode switching signal a control memory write completion signal supplied from a path controller, to said control memory unit in synchronization with the frame pulse.

Claim 7

A time switch with a dual memory structure-type control memory which utilizes at least two speech path switches, said switches having in common a timing synchronizing logic circuit, each switch comprising: a path controller for generating all control-memory-write completion output signals, said logic circuit detecting said output signals and producing mode-switching timing control signals; a control memory unit having a first memory in a hard cycle, which is a speech-control data read-only mode, and a second memory in a soft cycle, which is the mode for reading speech control data out of, or writing them into, a path controller, and means for switching the modes of said first and second memories in response to a mode switching signal; a speech memory unit having first and second memory elements controlled by said control memory unit, of which one memory element is set in the speech data write mode for writing frame-forming speech data in time slot units, and the other memory element is set in the speech data read mode for reading out one frame of speech data for each time slot, and means for switching the modes of said speech memory elements in synchronization with the frame formed speech data; and a mode-switching timing controller for synchronizing the mode-switching timing control signals supplied from said timing synchronizing logic circuit with the frame pulse determining the control data read timing of said control memory unit, and supplying said control signal to said control memory unit.

Claim 8

A time switch with a dual memory structure-type control memory which utilizes at least two speech path switches, said switches having in common a timing synchronizing logic circuit, each switch comprising: a path controller for generating all control-memory-write completion output signals, said logic circuit detecting said output signals and producing mode-switching timing control signals; a control memory unit having a first memory in a hard cycle, which is a speech-control data read-only mode, and a second memory in a soft cycle, which is the mode for reading speech control data out of, or writing them into, a path controller, and means for switching the modes of said first and second memories in response to a mode switching signal; a speech memory unit having first and second memory elements controlled by said control memory unit, of which one memory element is set in the speech data write mode for writing frame-forming speech data in time slot units, and the other memory element is set in the speech data read mode for reading out one frame of speech data for each time slot, and means for switching the modes of said speech memory elements in synchronization with the frame formed speech data; and a mode-switching timing controller for synchronizing the mode-switching timing control signals supplied from said timing synchronizing logic circuit with the frame pulse determining the control data read timing of said control memory unit, and supplying said control signal to said control memory unit.