DA converter testing system

Claim 2

A DA converter testing system comprising: a pattern generator which repeatedly generates digital codes to be applied to a test DA converter; first clock generating means which generates clock signals for regulating a period of pattern generation of the pattern generator; AD conversion means which receives the analog output signals of the test DA converter; second clock generating means which generates clock signals for regulating a conversion period of the AD conversion means so that the conversion period of the AD conversion means is greater than the waveform repeating period of the output repetitive waveform of the DA converter; memory means for storing data of the AD conversion means; and computing means for analyzing the data stored in the memory means.

Claim 3

A DA converter testing system as recited in claim 1, wherein waveform sampling means for sampling the output waveform of the DA converter in synchronism with the conversion period of the AD conversion means is provided between the test DA converter and the AD conversion means.

Claim 4

A DA converter testing system as recited in claim 1, wherein a low-pass filter is provided between the test DA converter and the AD conversion means.

Claim 5

A DA converter testing system as recited in claim 1, wherein said first clock generating means comprises a first frequency synthesizer which receives signals from a reference frequency oscillator means, and a first clock pulse generator which receives signals from the first frequency synthesizer, while said second clock generating means comprises a second frequency synthetsizer which receives signals from said reference frequency oscillator means, and a second clock pulse generator which receives signals from the second frequency synthesizer.

Claim 6

A DA converter testing system as recited in claim 3, wherein said first clock generating means comprises a frequency synthesizer which receives signals from a reference frequency oscillator means, and a clock pulse generator which receives signals from the frequency synthesizer, while said second clock generating means comprises a divider which receives signals from the clock pulse generator.

Claim 7

A DA converter testing system as recited in claim 5 further comprising a variable delay circuit which receives signals from the divider.

Claim 8

A DA converter testing system comprising: a pattern generator which repeatedly generates digital codes to be applied to a test DA converter; first clock generating means which generates clock signals for regulating a repetition period of the output digital codes of the pattern generator; waveform sampling means which receives the analog output signals of the test DA converter; AD converter means which receives the output signals of the waveform sampling means; sampling clock generating means which applies a clock signal of a period greater than the waveform repeating period of the analog output signals of the DA converter to the waveform sampling means and the AD conversion means; memory means for storing output data of the AD conversion means; and computing means which analyzes the output data of the AD conversion means stored in the memory means.

Claim 9

A DA converter testing system comprising: a pattern generator which repeatedly generates digital codes to be applied to a test DA converter; first clock generating means which generates clock signals for regulating a repetition period of the output digital codes of the pattern generator; waveform sampling means which receives the analog output signals of the test DA converter; AD converter means which receives the output signals of the waveform sampling means; sampling clock generating means which applies a clock signal of a period greater than the waveform repeating period of the analog output signals of the DA converter to the waveform sampling means and the AD conversion means; memory means for storing output data of the AD conversion means; and computing means which analyzes the output data of the AD conversion means stored in the memory means.

Claim 10

A DA converter testing system as recited in claim 7, wherein said clock generating means comprises a first frequency synthesizer which receives signals from a reference frequency oscillator means, and a clock pulse generator which receives signals from the first frequency synthesizer, while said sampling clock generating means comprises a second frequency synthesizer which receives signals from the reference frequency oscillator means, and a sampling clock generator which receives signals from the second frequency synthesizer.

Claim 11

A DA converter testing system as recited in claim 7, wherein said waveform sampling means comprises a sampling head, an amplifier which receives the output signals of the sampling head, and a sample-hold circuit which receives the output signals of the amplifier.

Claim 12

A DA converter testing system as recited in claim 7, wherein a frequency f in of a repetition frequency of the output digital codes of the pattern generator, a sampling frequency f SPL generated by the sampling clock generating means, a natural number n, a frequency Δf smaller than the sampling frequency f SPL meet an equation: Δf in =n f SPL +Δf.

Claim 13

A DA converter testing system comprising: a pattern generator which repeatedly generates digital codes to be applied to a test DA converter; clock generating means which generates clock signals for regulating a repetition period of the output digital codes of the pattern generator; first waveform sampling means which receives an analog output signal of the test DA converter; first AD conversion means which receives the output of the first waveform sampling means; second waveform sampling means which receives the output of the pattern generator; second AD conversion means which receives the output of the second waveform sampling means; sampling clock generating means which applies clocks of a period greater than the period of waveform repetition of the analog output signal of the test DA converter to the first waveform sampling means, the first AD conversion means, the second waveform sampling means and the second conversion means; memory means which stores the respective output data of the first AD conversion means and the second AD conversion means; and computing means which analyzes the data stored in the memory means.

Claim 14

A DA converter testing system comprising: a pattern generator which repeatedly generates digital codes to be applied to a test DA converter; clock generating means which generates clock signals for regulating a repetition period of the output digital codes of the pattern generator; first waveform sampling means which receives an analog output signal of the test DA converter; first AD conversion means which receives the output of the first waveform sampling means; second waveform sampling means which receives the output of the pattern generator; second AD conversion means which receives the output of the second waveform sampling means; sampling clock generating means which applies clocks of a period greater than the period of waveform repetition of the analog output signal of the test DA converter to the first waveform sampling means, the first AD conversion means, the second waveform sampling means and the second conversion means; memory means which stores the respective output data of the first AD conversion means and the second AD conversion means; and computing means which analyzes the data stored in the memory means.

Claim 15

A DA converter testing system as recited in claim 11, wherein said clock generating means comprises a first frequency synthesizer which receives signals from a reference frequency oscillator means, and a clock pulse generator which receives the output signals of the first frequency synthesizer; said sampling clock generating means comprises a second frequency synthesizer which receives signals from the reference frequency oscillator means, and a sampling clock pulse generator which receives the output signals of the second frequency synthesizer.

Claim 16

A DA converter testing system as recited in claim 11, wherein said first waveform sampling means comprises a sampling head, an amplifier which receives the output of the sampling head, and a sample-hold circuit which receives the output of the amplifier.

Claim 17

A DA converter testing system as recited in claim 11, wherein said second waveform sampling means comprises a sampling head, an amplifier which receives the output of the sampling head, and a sample-hold circuit which receives the output of the amplifier.

Claim 18

A DA converter testing system as recited in claim 11, wherein a frequency f in of a repetition of the output digital codes of the pattern generator, a sampling frequency f SPL generated by the sampling clock generating means, a natural number n, and a frequency Δf smaller than the sampling frequency f SPL meet an equation: Δf in =n f SPL +Δf.

Claim 19

A DA converter testing system as recited in claim 11, wherein a delay line is provided between said sampling clock generating means and said second waveform sampling means.