Counting circuit employing more equatably used plural counters for extended life

Claim 1

A counting circuit with non-volatile electrically erasable memory elements, said circuit comprising a plurality of similar counters, each of said counters having an input and a transfer output, each counter representing one place of a count; a plurality of non-volatile electrically erasable memory elements connected to respective ones of the counters; and connection means for switchably interconnecting said counters serially by the respective inputs and transfer outputs to form a series of the counters, counters near one end of the series being lower-value place counters, counters near a second end of the series being higher-value place counters, a switching of interconnections interchanging locations of counters in said series; and wherein counters for lower-value places of the count are cyclically connected to each other via their counter inputs and transfer outputs, association of the counters with respective places of the count being changed by said connection means as a function of a signal of the counter of a higher-value place of the count, said connection means including a memory addressable by a higher-value place counter for designating an arrangement of switching connections of the counters as a function of a higher-value place of a count of the counting circuit, a cyclical rearrangement of the counters allowing for more uniform usage of the counters and their respective memory elements.