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US4757438A Expired / Lapsed US ⏱️ 0.0 years remaining

Computer system enabling automatic memory management operations

Assignee: Texas Instruments Inc
•
Filing: 1984-07-12
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Granted: 1988-07-12
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Expires: 2004-07-12
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Abstract

Abstract A computer system is provided which enables automatic memory operations independently of a CPU. The computer system includes a virtual machine and a logical memory system which is accessed by the virtual machine through a binding register unit, enabling the virtual machine to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the virtual machine.

Inventors

  • 👤 Satish Thatte
  • 👤 Donald W. Oxley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 21:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0253; G06F12/08

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 139 words
A computer system, comprising: a memory having a logical address space which can be mapped onto a virtual address space, which can in turn be mapped onto a physical address space; and a virtual machine interconnected to the memory and serving to (1) interpret a set of instructions defining the virtual machine, and (2) translate logical addresses to virtual addresses for application to said memory, and including means for generating said set of virtual machine defining instructions, including allocating blocks of logical address space, writing data into and reading from the allocated logical address space, for performing an "EQ" test for determining if two pointers within the logical address space refer to the same block of allocated logical address space, and copying contents of a first logical address to a second logical address within the allocated logical address space.
Claim 2
Dependent Claim 139 words
A computer system, comprising: a memory having a logical address space which can be mapped onto a virtual address space, which can in turn be mapped onto a physical address space; and a virtual machine interconnected to the memory and serving to (1) interpret a set of instructions defining the virtual machine, and (2) translate logical addresses to virtual addresses for application to said memory, and including means for generating said set of virtual machine defining instructions, including allocating blocks of logical address space, writing data into and reading from the allocated logical address space, for performing an "EQ" test for determining if two pointers within the logical address space refer to the same block of allocated logical address space, and copying contents of a first logical address to a second logical address within the allocated logical address space.
Claim 3
Dependent Claim 28 words
The computer system of claim 1 wherein said virtual machine comprises a CPU and a set of binding registers for interfacing said CPU to said virtual address space.
Claim 4
Dependent Claim 27 words
The computer system of claim 2 wherein a logical address comprises at least a binding register designator to identify an associated block within the logical address space.
Claim 5
Dependent Claim 27 words
The computer system of claim 3 wherein said logical address further comprises a relative index to a location within the block pointed to by the designated register.
Claim 6
Dependent Claim 47 words
The computer system of claim 4 wherein said physical address space comprises a semiconductor memory, a disk memory, and a disk controller, whereby said virtual machine controls the operation of said disk controller to control the flow of information between said disk memory and said semiconductor memory.

References Cited (Backward Citations)

US3825904A Cited
US3938096A Cited
US4057848A Cited
US4047243A Cited
US4388685A Cited
US4459661A Cited
US4253145A Cited
US4410941A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-07-12 1992-01-11 1992-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-07-12 1996-01-11 1996-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-07-12 2000-01-11 2000-07-12 $7700.00 Window Closed / Lapsed

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