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Patent US4757273A successfully refreshed from Google Patents.
US4757273A
Expired / Lapsed
US
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Complementary transconductance amplifiers
Assignee: Individual
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Filing: 1987-07-13
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Granted: 1988-07-12
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Expires: 2007-07-13
Abstract
Abstract A complementary differential amplifier comprising a first and a second pair of complementary bipolar transistors, each of said transistors having a base, emitter and a collector, a resistor network for coupling said emitters, a first and a second level shift bias network, a resistor network for coupling said first and said second level shift bias networks to the bases of said first and said second pair of complementary transistors, a constant current source coupled between the level shift bias networks and a source of a first reference potential and a reference current generator coupled to the current source for generating a reference bias current for said first and said second level shift bias networks which is proportional to absolute temperature.
Inventors
- 👤 Derek Bray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:41
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
181 words
A circuit configuration which operates in a combined differential-complementary mode which is substantially linear over a predetermined range of operation comprising: a first and a second pair of complementary bipolar transistors, each of said transistors having a base, emitter, collector and a typical incremental emitter impedance having a value R e =(kT/qI e ), where k=Boltzmann Constant T=Absolute Temperature q=Electron Charge, and I e =Emitter Current; means for coupling said emitters; a first and a second level shift bias network, each of said networks comprising transistors which substantially match said complementary transistors; means for coupling said first and said second level shift bias networks to the bases of said first and said second pair of complementary transistors, respectively; means for providing a current coupled between said level shift bias networks and a source of a first reference potential; and means for generating a second reference potential (V ref ) which is coupled to said current providing means for generating a reference bias current for said first and said second level shift bias networks, said bias current being proportional to absolute temperature.
Claim 2
Dependent Claim
181 words
A circuit configuration which operates in a combined differential-complementary mode which is substantially linear over a predetermined range of operation comprising: a first and a second pair of complementary bipolar transistors, each of said transistors having a base, emitter, collector and a typical incremental emitter impedance having a value R e =(kT/qI e ), where k=Boltzmann Constant T=Absolute Temperature q=Electron Charge, and I e =Emitter Current; means for coupling said emitters; a first and a second level shift bias network, each of said networks comprising transistors which substantially match said complementary transistors; means for coupling said first and said second level shift bias networks to the bases of said first and said second pair of complementary transistors, respectively; means for providing a current coupled between said level shift bias networks and a source of a first reference potential; and means for generating a second reference potential (V ref ) which is coupled to said current providing means for generating a reference bias current for said first and said second level shift bias networks, said bias current being proportional to absolute temperature.
Claim 3
Dependent Claim
23 words
A circuit configuration according to claim 1 comprising: means coupling said level shift bias networks together for defining said predetermined range of operation.
Claim 4
Dependent Claim
18 words
A circuit configuration according to claim 2 wherein said range of operation defining means comprises a resistance means.
Claim 5
Dependent Claim
16 words
A circuit configuration according to claim 1 wherein said emitter coupling means comprises a resistor network.
Claim 6
Dependent Claim
74 words
A circuit configuration according to claim 1 wherein each of said first and said second pair of complementary bipolar transistors comprises an NPN transistor and a PNP transistor, said emitter coupling means comprises a resistance having a value R E coupled between the emitters of said NPN transistors and the emitters of said PNP transistors, respectively, and said value R e is substantially equal to said value R E at all normal operating temperatures.
Claim 7
Dependent Claim
145 words
A circuit configuration according to claim 1 wherein each of said first and said second pair of complementary bipolar transistors comprises an NPN transistor and a PNP transistor, said emitter coupling means comprises a first, second, third, fourth and fifth resistances, each of said first, second, third and fourth resistances having a value R E and said fifth resistance having a value R g ; means for coupling said first and said second resistances in series between the emitters of said first pair of complementary bipolar transistors; means for coupling said third and fourth resistances in series between the emitters of said second pair of complementary bipolar transistors; and means for coupling said fifth resistance between said first and second and said third and fourth resistances, respectively; and said value R e is substantially equal to said value R E at all normal operating temperatures.
Claim 8
Dependent Claim
143 words
A circuit configuration according to claim 1 wherein each of said first and said second pair of complementary bipolar transistors comprises an NPN transistor and a PNP transistor, said emitter coupling means comprises a first, second, third, fourth and fifth resistance, each of said first, second, third and fourth resistances having a value a·R E and said fifth resistance having a value R E (1-a), where (a) comprises a variable; means for coupling said first and said second resistances in series between said emitters of said NPN transistors; means for coupling said third and fourth resistances in series between said emitters of said PNP transistors; and means for coupling said fifth resistance between said first and second resistances and said third and fourth resistances, respectively, and said value R e is substantially equal to said value R E at all normal operating temperatures.
Claim 9
Dependent Claim
111 words
A circuit configuration according to claim 1 wherein each of said level shift bias networks comprises a third pair of complementary transistors, each of said third pair of transistors having a collector, a base and an emitter; means for coupling said emitters in said third pair together; means for applying an input signal to the base of one of said complementary transistors in said third pair; means for coupling the base and collector of the other of said complementary transistors in said third pair; and means for coupling the bases of both of said complementary transistors in said third pair to one of said first and second pairs of complementary transistors.
Claim 10
Dependent Claim
22 words
A circuit configuration according to claim 8 wherein said emitter coupling means in each of said bias networks comprises a resistance means.
Claim 11
Dependent Claim
63 words
A circuit configuration according to claim 1 wherein said current providing means comprises: a first current source coupled between said first network and said source of said first reference potential; a second current source coupled between said second network and said source of said first reference potential; and means coupling said level shift bias networks together for defining said predetermined range of operation.
Claim 12
Dependent Claim
33 words
A circuit configuration according to claim 1 wherein said current providing means comprises; a single current source; and means coupling said current source to said networks for defining said predetermined range of operation.
Claim 13
Dependent Claim
15 words
A circuit configuration according to claim 11 wherein said range defining means comprise resistance means.
References Cited (Backward Citations)
US4229705A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |