Digitized quadrature phase shift keying modulator

Claim 2

A digitized quadrature phase shift keying modulator comprising: digital filter means including a look-up table for receiving as parallel data digital I data and digital Q data representing quadrature phase shift keying data and for generating impulse response waveforms represented by plural sampling points for each bit of the I data and Q data bit by bit; interpolating means for re-sampling each impulse response waveform of each of the I data and Q data generated from said digital filter means and for interpolating an interval between adjacent sampling points with I and Q data to thereby change the sampling rate; means for extracting, at different timings, each of the interpolated I data and Q data from said interpolating means at every other sample; means for synthesizing the extracted I data and Q data from said extracting means; and digital to analog converter means for converting the output digital data from said synthesizing means into an analog signal.

Claim 3

A digitized quadrature phase shift keying modulator according to claim 1 wherein said means for synthesizing the extracted I data and Q data comprises: code inversion means for effecting code conversion of each of the extracted I data and a Q data from said extracting means on every other sampling period; and an adder for adding together the code inverted I data and Q data from said code inversion means.

Claim 4

A digitized quadrature phase shift keying modulator according to claim 1 wherein said means for synthesizing the extracted I data and Q data comprises: an adder for adding together the extracted I data and Q data from said extracting means; and code inversion means for handing two samples of data from said adder as a set and for performing performing code inversion of the data for every other set.

Claim 5

A digitized quadrature phase shift keying modulator according to claim 1 wherein said interpolating means comprises: a subtractor for computing a difference between two adjacent samples of the I data or Q data from said digital filter; a divider for dividing the computed difference from said subtracter by the number of interpolations m; an adder connected to receive two inputs wherein one input is the dividing result of said divider for adding the one input to another input and then outputting the result of the addition; and selector means connected to receive the input of said subtractor and the output said adder for selectively outputting either said input of said subtracter or the output of said adder as an output sample value, said output sample value being fed back to said adder as said another input to be added to said dividing result.

Claim 6

A digitized quadrature phase shift keying modulator according to claim 1 wherein said extracting means comprises: a first flip-flop for fetching the interpolated I data from said interpolating means at a period which is half the re-sampling period; and a second flip-flop operative to fetch the interpolated Q data from said interpolating means at a timing which displaces by half the period of said first flip-flop.

Claim 7

A digitized quadrature phase shift keying modulator comprising: a first selector for sequentially fetching parallel data of digital I data and digital Q data of quadrature phase shift keying and delivering serial digital data; a digital filter with look-up table having a read only memory (ROM) for receiving at its addresses the output data from said first selector and sampling n times the received data bit by bit to generate waveforms of impulse response of n samples/symbol; a second selector for sequentially separating the impulse response waveforms of said digital filter sample by sample to provide I data and Q data; interpolating means for re-sampling each impulse responsive waveform of each of said I data and Q data generated from said second selector and interpolating an interval between adjacent sampling points with (m-1) data to produce impulse response waveforms of (m×n) samples/symbol, where m is an intergral number of divisions in an interpolation period; means for extracting, at different timings, each of the interpolated I data and Q data from said interpolating means every other sample; means for synthesizing the extracted I data and Q data from said extracting means; and a digital to analog converter for converting the output digital data from said synchronizing means into an analog signal.

Claim 8

A digitized quadrature phase shift keying modulator comprising: a first selector for sequentially fetching parallel data of digital I data and digital Q data of quadrature phase shift keying and delivering serial digital data; a digital filter with look-up table having a read only memory (ROM) for receiving at its addresses the output data from said first selector and sampling n times the received data bit by bit to generate waveforms of impulse response of n samples/symbol; a second selector for sequentially separating the impulse response waveforms of said digital filter sample by sample to provide I data and Q data; interpolating means for re-sampling each impulse responsive waveform of each of said I data and Q data generated from said second selector and interpolating an interval between adjacent sampling points with (m-1) data to produce impulse response waveforms of (m×n) samples/symbol, where m is an intergral number of divisions in an interpolation period; means for extracting, at different timings, each of the interpolated I data and Q data from said interpolating means every other sample; means for synthesizing the extracted I data and Q data from said extracting means; and a digital to analog converter for converting the output digital data from said synchronizing means into an analog signal.

Claim 9

A quadrature phase shift keying modulator according to claim 6 further comprising a circuit, preceding said first selector, for delaying one of the I data and Q data relative to the other by half the cycle, wherein the sampling number n of said digital filter is selected to be an even number.