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US4754314A Expired / Lapsed US ⏱️ 0.0 years remaining

Split-level CMOS

Assignee: Texas Instruments Inc
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Filing: 1987-01-28
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Granted: 1988-06-28
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Expires: 2007-01-28
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Abstract

Abstract A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Inventors

  • 👤 David B. Scott
  • 👤 Satwinder S. Malhi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:52
CPC Classifications
H; H10; H10D; H10D88/00; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D88/01

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 130 words
A CMOS integrated circuit, comprising: (a) a single crystal semiconductor substrate; (b) a field oxide defining a moat in said substrate; (c) a continuous layer of semiconductor material contacting said substrate and extending over said field oxide, said layer forming a single crystal extension of said substrate in the regions contiguous thereto and forming a semiconductor device quality portion in the regions contiguous to said field oxide; (d) an insulated gate field effect transistor formed in said extension of said substrate of a predetermined channel conductivity type; (e) an insulated gate field effect transistor formed in said layer over said field oxide of the opposite channel conductivity type; and (f) a source/drain region of one of said transistors being contiguous to a source/drain region of the other of said transistors.
Claim 2
Dependent Claim 130 words
A CMOS integrated circuit, comprising: (a) a single crystal semiconductor substrate; (b) a field oxide defining a moat in said substrate; (c) a continuous layer of semiconductor material contacting said substrate and extending over said field oxide, said layer forming a single crystal extension of said substrate in the regions contiguous thereto and forming a semiconductor device quality portion in the regions contiguous to said field oxide; (d) an insulated gate field effect transistor formed in said extension of said substrate of a predetermined channel conductivity type; (e) an insulated gate field effect transistor formed in said layer over said field oxide of the opposite channel conductivity type; and (f) a source/drain region of one of said transistors being contiguous to a source/drain region of the other of said transistors.
Claim 3
Dependent Claim 25 words
A CMOS circuit as set forth in claim 1 wherein said predetermined channel conductivity type is N-type and said opposite channel conductivity type is P-type.
Claim 4
Dependent Claim 18 words
A CMOS circuit as set forth in claim 1 further including an insulating layer disposed over said transistors.
Claim 5
Dependent Claim 18 words
A CMOS circuit as set forth in claim 2 further including an insulating layer disposed over said transistors.
Claim 6
Dependent Claim 25 words
A CMOS circuit as set forth in claim 3 further including contact means extending through said insulating layer and contacting a said source/drain region thereunder.
Claim 7
Dependent Claim 25 words
A CMOS circuit as set forth in claim 4 further including contact means extending through said insulating layer and contacting a said source/drain region thereunder.

References Cited (Backward Citations)

JPS5497384A Cited
US4333099A Cited
JPS5743455A Cited
US4472729A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-06-28 1991-12-28 1992-06-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-06-28 1995-12-28 1996-06-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-06-28 1999-12-28 2000-06-28 $7700.00 Window Closed / Lapsed

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