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US4752748A
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Intelligent phase-locked loop
Assignee: Fujitsu IT Holdings Inc
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Filing: 1987-04-16
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Granted: 1988-06-21
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Expires: 2007-04-16
Abstract
Abstract An intelligent phase-locked loop performs adaptive transfer function parameter selection and fault tolerant self-monitoring within the phase error filtering algorithm. The algorithm includes a capture mode, at least one align mode and an operate mode. The capture mode shifts to the align mode if the phase error limit is not exceeded at the end of a first period of time. The align mode switches back to the capture mode if a reverse phase error relation is met during the mode. At the end of the align mode, the algorithm switches to the operate mode if a forward phase error relation is met. The operate mode continues indefinitely. However, a switchback to the align mode is made if an out of lock phase error limit is exceeded for the operate mode. The bandwidths of the transfer function of the loop are adapted for each of the modes so that the capture mode is the broadest bandwidth, the align mode is an intermediate bandwidth and the operate mode is a narrow bandwidth. Further, according to the invention, the algorithm performs hardware fault monitoring based on statistical processing carried out during the phase error filtering cycle.
Inventors
- 👤 Miroslaw Grzeszykowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:52
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/10; H03L7/107; H03L7/1075; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
293 words
In a phase locked loop apparatus having a variable frequency oscillator responsive to a control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating the control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, a method for processing the phase error signals to generate the control signal, comprising for mode M the steps of: (1) accumulating phase error signals for a preselected signal processing interval; (2) generating the control signal according to the transfer function over the phase error signals accumulated during the signal processing interval; (3) if M is greater than 1, testing the accumulated phase error signals against a loss-of-lock phase error limit for the mode M, and if the loss-of-lock phase error limit is exceeded, then shifting to mode M-1; and (4) if M is less than m, repeating steps 1, 2, and 3 for a mode time limit for the mode M, and then, proceeding to step 5, or if M=m, repeating steps 1, 2, and 3; (5) testing the accumulated phase error signals to determine whether an end-of-mode phase error limit for the mode M is exceeded, and if the end-of-mode phase error limit is not exceeded, then shifting to mode M+1.
Claim 2
Dependent Claim
293 words
In a phase locked loop apparatus having a variable frequency oscillator responsive to a control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating the control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, a method for processing the phase error signals to generate the control signal, comprising for mode M the steps of: (1) accumulating phase error signals for a preselected signal processing interval; (2) generating the control signal according to the transfer function over the phase error signals accumulated during the signal processing interval; (3) if M is greater than 1, testing the accumulated phase error signals against a loss-of-lock phase error limit for the mode M, and if the loss-of-lock phase error limit is exceeded, then shifting to mode M-1; and (4) if M is less than m, repeating steps 1, 2, and 3 for a mode time limit for the mode M, and then, proceeding to step 5, or if M=m, repeating steps 1, 2, and 3; (5) testing the accumulated phase error signals to determine whether an end-of-mode phase error limit for the mode M is exceeded, and if the end-of-mode phase error limit is not exceeded, then shifting to mode M+1.
Claim 3
Dependent Claim
40 words
The method of claim 1, further including the step after the step of testing the end-of-mode phase error limit of: if the end-of-mode phase error limit is exceeded, and if M is between 1 and m, shifting to mode M-1.
Claim 4
Dependent Claim
41 words
The method of claim 1, further including the step after the step of testing the end-of-mode phase error limit of: if the end-of-mode phase error limit is exceeded, and if M is between 1 and m, remaining in the mode M.
Claim 5
Dependent Claim
37 words
The method of claim 1, further including, after the step of testing the end-of-mode phase error limit, the step of: if the end-of-mode phase error limit is exceeded, and if M equals 1, remaining in mode M.
Claim 6
Dependent Claim
113 words
The method of claim 1, wherein the phase detector further includes means for detecting faults in the external reference signal and generates fault signals and the processor includes means for storing the frequency control signal generated during a previous signal processing interval, and further including the steps of: (1) accumulating fault signals generated during a current signal processing interval; (2) performing statistical analysis of the accumulated fault signals during signal processing interval; and (3) in response to the analysis of the accumulated fault signals, transferring the frequency control signal generated during the current signal processing interval or the frequency control signal generated during a previous signal processing interval to the variable frequency oscillator.
Claim 7
Dependent Claim
18 words
The method of claim 1, further including the step of interpolating the control signal during signal processing intervals.
Claim 8
Dependent Claim
171 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein an improvement comprises: means, in the phase error processor, for changing mode M to mode M+1 according to a forward relation and for changing mode M to mode M-1 according to a reverse relation, the forward and reverse relations establishing hysteresis.
Claim 9
Dependent Claim
171 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein an improvement comprises: means, in the phase error processor, for changing mode M to mode M+1 according to a forward relation and for changing mode M to mode M-1 according to a reverse relation, the forward and reverse relations establishing hysteresis.
Claim 10
Dependent Claim
174 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein the processor comprises: means for changing mode M to mode M+1 according to a forward relation based on a first set of parameters; and means for changing mode M to mode M-1 according to a reverse relation based on a second set of parameters.
Claim 11
Dependent Claim
174 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein the processor comprises: means for changing mode M to mode M+1 according to a forward relation based on a first set of parameters; and means for changing mode M to mode M-1 according to a reverse relation based on a second set of parameters.
Claim 12
Dependent Claim
21 words
The apparatus of claim 8, wherein the first set of parameters and the second set of parameters are not identical sets.
Claim 13
Dependent Claim
32 words
The apparatus of claim 8, wherein the first set of parameters comprises a mode duration time limit and an end-of-mode phase error limit for mode M, where M is less than m.
Claim 14
Dependent Claim
26 words
The apparatus of claim 8, wherein the second set of parameters comprises a loss-of-lock phase error limit for mode M, where M is greater than 1.
Claim 15
Dependent Claim
33 words
The apparatus of claim 11, wherein the second set of parameters further includes the end-of-mode phase error limit and mode duration time limit for mode M, where M is between 1 and m.
Claim 16
Dependent Claim
110 words
The apparatus of claim 8, wherein the phase detector further includes means for detecting faults in the external reference signal and generates fault signals and the processor further includes: means for storing the control signal generated during a previous signal processing interval; means for accumulating fault signals generated during a current signal processing interval; means for performing statistical analysis of the accumulated fault signals during current signal processing interval; and means, responsive to the analysis of the accumulated fault signals, for transferring the frequency control signal generated during the current signal processing interval or the frequency control signal generated during a previous signal processing interval to the variable frequency oscillator.
Claim 17
Dependent Claim
110 words
The apparatus of claim 8, wherein the processor implements the reverse relation for mode M, where M is greater than 1, by testing the phase error signals against a loss-of-lock phase error limit for the mode M, and if the loss-of-lock phase error limit is exceeded, then shifting to mode M-1; and wherein the processor implements the forward relation for mode M, where M is less than m, by testing at a mode time limit for mode M the phase error signals to determine whether an end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is not exceeded, then shifting to mode M+1.
Claim 18
Dependent Claim
64 words
The apparatus of claim 14, wherein the processor further implements the reverse relation for mode M, where M is between 1 and m, by testing at the mode time limit for mode M the phase error signals to determine whether the end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is exceeded, then shifting to mode M-1.
Claim 19
Dependent Claim
277 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein the processor comprises: means, for mode M, where M is greater than 1, for testing the phase error signals against a loss-of-lock phase error limit for mode M, and if the loss-of-lock phase error limit is exceeded, then shifting to mode M-1; means, for mode M, where M is less than m, for testing at a mode time limit for mode M the phase error signals to determine whether an end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is not exceeded, then shifting to mode M+1; and means, for mode M, where M is between 1 and m, for testing at the mode time limit for mode M the phase error signals to determine whether the end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is exceeded, then shifting to mode M-1.
Claim 20
Dependent Claim
277 words
A phase-locked loop apparatus comprising a variable frequency oscillator responsive to the control signal for generating a loop reference signal, a phase detector receiving an external reference signal and the loop reference signal and generating phase error signals, and a phase error processor receiving the phase error signals and generating a control signal according to a transfer function having modes 1 to m, where m is at least 3, and where mode M, for M equal to 1, is adapted for quick alignment of the loop reference signal with the external reference signal, mode M for M between 1 and m, is adapted for stabilization of the loop reference signal, and mode M for M equal to m, is adapted for normal operation of the phase locked loop, and wherein the processor comprises: means, for mode M, where M is greater than 1, for testing the phase error signals against a loss-of-lock phase error limit for mode M, and if the loss-of-lock phase error limit is exceeded, then shifting to mode M-1; means, for mode M, where M is less than m, for testing at a mode time limit for mode M the phase error signals to determine whether an end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is not exceeded, then shifting to mode M+1; and means, for mode M, where M is between 1 and m, for testing at the mode time limit for mode M the phase error signals to determine whether the end-of-mode phase error limit for mode M is exceeded, and if the end-of-mode phase error limit is exceeded, then shifting to mode M-1.
Claim 21
Dependent Claim
110 words
The apparatus of claim 16, wherein the phase detector further includes means for detecting faults in the external reference signal and generates fault signals and the processor further includes: means for storing the control signal generated during a previous signal processing interval; means for accumulating fault signals generated during a current signal processing interval; means for performing statistical analysis of the accumulated fault signals during current signal processing interval; and means, responsive to the analysis of the accumulated fault signals, for transferring the frequency control signal generated during the current signal processing interval or the frequency control signal generated during a previous signal processing interval to the variable frequency oscillator.
References Cited (Backward Citations)
US4513429A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-21 | 1991-12-21 | 1992-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-21 | 1995-12-21 | 1996-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-21 | 1999-12-21 | 2000-06-21 | $7700.00 | Window Closed / Lapsed |