Self-aligned contacts for bipolar process

Claim 2

A process of manufacturing a semiconductor device comprising: (a) providing a substrate having a first surface; (b) providing a first dielectric layer over said first surface of said substrate; (c) selectively removing a portion of said first dielectric layer and exposing a selected area of said substrate; (d) providing a first conductive layer over said first dielectric layer and said exposed substrate; (e) providing a second dielectric layer over said first conductive layer; (f) patterning said second dielectric layer, and using said dielectric layer as a mask for patterning said first conductive layer; (g) patterning said first conductive layer and exposing side surfaces of said first conductive layer; (h) heating said second dielectric layer to a predetermined temperature such that said second dielectric layer flows and covers said side surfaces of said first conductive layer; (i) removing said first dielectric layer from a contact area; and (j) providing a second conductive layer to said contact area.

Claim 3

The process of claim 1, wherein said predetermined temperature is lower than a melting temperature of said first dielectric layer and said first conductive layer.

Claim 4

The process of claim 2, further comprising providing an epitaxial layer of a first conductivity type on said first surface of said substrate prior to providing said first dielectric layer, said first dielectric layer being provided on a first surface of said epitaxial layer.

Claim 5

The process of claim 3, further comprising providing a base region of a second conductivity type in said epitaxial layer prior to providing said first dielectric layer.

Claim 6

The process of claim 4, wherein said conductive layer includes a polycrystalline silicon, said process further comprising providing dopants of a first conductivity type in said polycrystalline silicon layer prior to providing said second dielectric layer.

Claim 7

The process of claim 5, wherein said second dielectric layer includes a doped silica glass, wherein said heating for flowing said doped silica glass includes heating said glass to approximately 900° C. for a period of time such that said glass flows and covers said side surfaces of said first conductivity layer.

Claim 8

The process of claim 6, wherein said epitaxial layer and said substrate include silicon and said second conductive layer includes a salicide, said salicide providing a self-aligned interconnecting contact to said base region.

Claim 9

The process of claim 6, wherein said second conductive layer includes a metal, said metal providing a self-aligned interconnecting contact to said base region.

Claim 10

The process of claim 6, wherein said substrate includes said first conductivity type and forms a collector region, said process further comprising providing a contact to said substrate.

Claim 11

The process of claim 6, further comprising providing dopants of a second conductivity type in said epitaxial layer for forming a collector region.

Claim 12

The process of claim 6, further comprising providing an oxide layer on a top surface of said conductive layer before providing said doped silica glass thereon, wherein said composite silica glass and oxide are patterned for exposing said selected areas of said conductive layer thereunder.

Claim 13

A process for forming a bipolar semiconductor wafer comprising the steps of: (a) providing a substrate of a first conductivity type; (b) selectively forming a plurality of field oxide regions on a first surface of said substrate such that an active region is defined between said field oxide regions, wherein said first surface of said substrate is exposed in said active area region; (c) providing a base region of a second conductivity type in said substrate within substantially said active region; (d) selectively forming a thin oxide layer on a portion of said first surface of said substrate in said active region such that an emitter region is defined between said thin oxide layer, wherein said first surface of said substrate is exposed in said emitter region; (e) providing a polycrystalline silicon layer over said thin oxide layer and said exposed first surface of said substrate; (f) providing a first dielectric layer over said polycrystalline silicon layer, wherein said dielectric layer flows when heated to a preselected temperature; (g) selectively removing said first dielectric layer and exposing selected areas of said polycrystalline silicon layer; (h) selectively removing said exposed regions of said polycrystalline layer and exposing selected areas of said thin oxide layer, wherein side surfaces of said polycrystalline layer are exposed as a result of said removal of said exposed regions thereof; (i) heating said dielectric layer to said preselected temperature for causing said dielectric layer to flow and cover said exposed side surfaces of said polycrystalline layer; (j) selectively removing said exposed thin oxide and exposing said first surface of said substrate; and (k) selectively providing a second conductive layer over said exposed portions of said substrate.

Claim 14

A process for forming a bipolar semiconductor wafer comprising the steps of: (a) providing a substrate of a first conductivity type; (b) selectively forming a plurality of field oxide regions on a first surface of said substrate such that an active region is defined between said field oxide regions, wherein said first surface of said substrate is exposed in said active area region; (c) providing a base region of a second conductivity type in said substrate within substantially said active region; (d) selectively forming a thin oxide layer on a portion of said first surface of said substrate in said active region such that an emitter region is defined between said thin oxide layer, wherein said first surface of said substrate is exposed in said emitter region; (e) providing a polycrystalline silicon layer over said thin oxide layer and said exposed first surface of said substrate; (f) providing a first dielectric layer over said polycrystalline silicon layer, wherein said dielectric layer flows when heated to a preselected temperature; (g) selectively removing said first dielectric layer and exposing selected areas of said polycrystalline silicon layer; (h) selectively removing said exposed regions of said polycrystalline layer and exposing selected areas of said thin oxide layer, wherein side surfaces of said polycrystalline layer are exposed as a result of said removal of said exposed regions thereof; (i) heating said dielectric layer to said preselected temperature for causing said dielectric layer to flow and cover said exposed side surfaces of said polycrystalline layer; (j) selectively removing said exposed thin oxide and exposing said first surface of said substrate; and (k) selectively providing a second conductive layer over said exposed portions of said substrate.

Claim 15

The process of claim 12, wherein said dielectric layer includes a flowable doped silica glass having a flowable temperature which is lower than a melting temperature of said thin oxide layers and said polycrystalline silicon layer.

Claim 16

The process of claim 13, further comprising providing dopants of a second conductivity type in said polycrystalline silicon layer for forming said emitter prior providing said first dielectric layer over said polycrystalline silicon layer.

Claim 17

The process of claim 14, wherein said heating said dielectric layer includes heating said doped silica glass to approximately 900° C. wherein said heating causes said doped silica glass to flow over the exposed surfaces of said polycrystalline silicon layer, said heating further causing said dopants in said polycrystalline layer to diffuse into said substrate whereby a shallow emitter region is formed therein.

Claim 18

The process of claim 15, further comprising providing a shallow region of said second conductivity type in said substrate immediately under said thin oxide layers after selectively removing said exposed regions of said polycrystalline layer.

Claim 19

The process of claim 16, wherein said substrate includes silicon and said second conductive layer includes a silicide, said silicide providing interconnecting contacts to said base region, said shallow regions of said second conductivity type reducing resistance between said contacts and said base region.

Claim 20

The process of claim 16, wherein said substrate includes silicon and said second conductive layer includes a salicide, said salicide providing interconnecting contacts to said base region, said shallow regions of said second conductivity type reducing resistance between said contacts and said base region.

Claim 21

The process of claim 16, wherein said substrate includes silicon and said second conductive layer includes a metal, said metal providing interconnecting contacts to said base region, said shallow regions of said second conductivity type reducing resistance between said contacts and said base region.

Claim 22

The process of claim 16, further comprising providing a second oxide layer on said polycrystalline layer before providing said doped silica glass thereon, wherein said composite silica glass and second oxide layer are patterned and etched for exposing said polycrystalline layer thereunder.