Patent US4751458A successfully refreshed from Google Patents.
US4751458A
Expired / Lapsed
US
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Test pads for integrated circuit chips
Assignee: Nokia Bell Labs
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Filing: 1985-09-27
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Granted: 1988-06-14
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Expires: 2005-09-27
Abstract
Abstract Integrated circuit chips included on a wafer typically include multiple internal test pads. During diagnostic testing of the wafer, a fine-point test probe is utilized to contact the pads. As feature sizes decrease, the task of consistently and reliably probing very-small-area internal test pads becomes increasingly difficult and time-consuming. In accordance with a feature of the present invention, each internal test pad on a chip is designed to include an interior opening. This provides a continuous interior edge which reliably limits sliding of an inserted tip while ensuring good electrical contact between the tip and the pad being probed.
Inventors
- 👤 John P. Elward, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:32
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
156 words
For use in manufacturing an integrated circuit chip structure of the type that includes a conductive pattern formed on an insulating layer, the pattern including at least one test pad which comprises an interior recessed portion having a continuous internal edge, a method comprising the step of inserting the point of an inclined test probe into said interior portion from any direction to slide said point across the bottom surface of said portion into electrical contact with the internal edge of said pad; wherein the longitudinal axis of said probe is oriented at an angle of approximately 30-to-45 degrees with respect to the surface of said pad; wherein said test pad is located away from the edges of said chip structure in an interior region of the structure; wherein said portion comprises an interior opening in said pad; and wherein the interior opening in said pad reveals a portion of the surface of said insulating layer.
Claim 2
Dependent Claim
156 words
For use in manufacturing an integrated circuit chip structure of the type that includes a conductive pattern formed on an insulating layer, the pattern including at least one test pad which comprises an interior recessed portion having a continuous internal edge, a method comprising the step of inserting the point of an inclined test probe into said interior portion from any direction to slide said point across the bottom surface of said portion into electrical contact with the internal edge of said pad; wherein the longitudinal axis of said probe is oriented at an angle of approximately 30-to-45 degrees with respect to the surface of said pad; wherein said test pad is located away from the edges of said chip structure in an interior region of the structure; wherein said portion comprises an interior opening in said pad; and wherein the interior opening in said pad reveals a portion of the surface of said insulating layer.
Claim 3
Dependent Claim
17 words
A method as in claim 1 wherein the internal edge of said interior opening is substantially vertical.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |