← Back to Patent Explorer
US4750081A Expired / Lapsed US ⏱️ 0.0 years remaining

Phantom ESD protection circuit employing E-field crowding

Assignee: Unisys Corp
•
Filing: 1987-10-19
•
Granted: 1988-06-07
•
Expires: 2007-10-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated circuit chip having improved static discharge protection comprises a semiconductor substrate with a major surface, a plurality of transistors that are integrated into the surface, patterned conductors that interconnect the transistors and route input signals to the transistors, with the patterned conductors including metal pads for receiving the input signals from an external source; wherein the improvement comprises respective diodes which are integrated into the surface directly beneath the metal pads, and which connect the pads to the substrate and conduct electrostatic charge therebetween. With this structure, no additional chip space is required over that which is used by the transistors which are being protected since the diodes are hidden in the normally unused chip space beneath the pads. Also with this structure, the diodes can be large since the metal pads are inherently large enough to receive a bonding wire; and thus the diodes have a large current-carrying capacity and a small series resistance. Preferably, the metal pads have sharp corners of 90° or less which tend to accumulate any electrostatic charge, and the diodes are disposed beneath the metal pads at these corners. Since the diodes are located where the charge tends to accumulate, they are more effective in dissipating that charge than if they were located elsewhere.

Inventors

  • 👤 Xiaonan Zhang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 10:43
CPC Classifications
H; H10; H10W; H10W42/00; H10W42/60

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 89 words
An integrated circuit chip, having improved static discharge protection, comprising: a semiconductor substrate with a major surface; a plurality of bipolar transistors that are integrated into said surface; patterned conductors that interconnect said bipolar transistors and route input signals to the base of selected ones of said bipolar transistors; said patterned conductors including metal pads for receiving said input signals for an external source; wherein integrated into said surface directly beneath said metal pads are respective diodes which connect said pads to said substrate and conduct electrostatic charge therebetween.
Claim 2
Dependent Claim 89 words
An integrated circuit chip, having improved static discharge protection, comprising: a semiconductor substrate with a major surface; a plurality of bipolar transistors that are integrated into said surface; patterned conductors that interconnect said bipolar transistors and route input signals to the base of selected ones of said bipolar transistors; said patterned conductors including metal pads for receiving said input signals for an external source; wherein integrated into said surface directly beneath said metal pads are respective diodes which connect said pads to said substrate and conduct electrostatic charge therebetween.
Claim 3
Dependent Claim 29 words
An integrated circuit chip according to claim 1 wherein each of said metal pads has an acute corner, with a respective one of said diodes disposed at said corner.
Claim 4
Dependent Claim 23 words
An integrated circuit chip according to claim 1 wherein each pad has four corners of 90°, and respective diodes lie at each corner.
Claim 5
Dependent Claim 21 words
An integrated circuit chip according to claim 1 wherein a plurality of said diodes lie beneath each pad along its perimiter.
Claim 6
Dependent Claim 47 words
An integrated circuit chip according to claim 1 wherein said transistors are isolated from each other by a channel stop; and said diodes are P + N + junctions which are patterned by two masks that also pattern said channel stop and the collector of said transistors.
Claim 7
Dependent Claim 34 words
An integrated circuit chip according to claim 1 wherein each of said pads is at least 50 μm by 50 μm, and each of said diodes is at least 10 μm by 10 μm.
Claim 8
Dependent Claim 81 words
An integrated circuit chip, having improved static discharge protection, comprising: a semiconductor substrate with a major surface; a plurality of transistors that are integrated into said surface; patterned conductors that interconnect said transistors and route input signals to selected ones of said transistors; said patterned conductors including pads for receiving said input signals for an external source; wherein integrated into said surface directly beneath said pads are respective diodes which connect said pads to said substrate and conduct electrostatic charge therebetween.
Claim 9
Dependent Claim 81 words
An integrated circuit chip, having improved static discharge protection, comprising: a semiconductor substrate with a major surface; a plurality of transistors that are integrated into said surface; patterned conductors that interconnect said transistors and route input signals to selected ones of said transistors; said patterned conductors including pads for receiving said input signals for an external source; wherein integrated into said surface directly beneath said pads are respective diodes which connect said pads to said substrate and conduct electrostatic charge therebetween.
Claim 10
Dependent Claim 14 words
An integrated circuit chip according to claim 7 wherein said transistors are bipolar transistors.
Claim 11
Dependent Claim 14 words
An integrated circuit chip according to claim 7 wherein said transistors are NMOS transistors.
Claim 12
Dependent Claim 14 words
An integrated circuit chip according to claim 7 wherein said transistors are CMOS transistors.
Claim 13
Dependent Claim 26 words
An integrated circuit chip according to claim 7 wherein each of said pads has an acute corner with a respective one of said diodes disposed thereunder.

References Cited (Backward Citations)

US4106048A Cited
US4481421A Cited
US4605980A Cited
US4692781A Cited
US4692781B1 Cited
US4692781B2 Cited
US4686602A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-06-07 1991-12-07 1992-06-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-06-07 1995-12-07 1996-06-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-06-07 1999-12-07 2000-06-07 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag