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US4750078A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor protection circuit having both positive and negative high voltage protection

Assignee: NXP USA Inc
•
Filing: 1987-06-15
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Granted: 1988-06-07
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Expires: 2007-06-15
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Abstract

Abstract An input protection circuit is provided which prevents positive and negative voltages significantly higher than a supply voltage potential from damaging operational circuitry connected to an input terminal. A bipolar transistor has current conducting electrodes connected between the supply voltage and the input terminal. A first MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and collector of the bipolar transistor in response to the sign and magnitude of an input signal. A second MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and emitter of the bipolar transistor in responses to the sign and magnitude of the input signal.

Inventors

  • 👤 Jeffrey D. Ganger
  • 👤 Jeff D. Stump

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 17:33
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08126

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 146 words
A semiconductor protection circuit coupled to an input terminal of an operational circuit for preventing positive and negative voltages exceeding a predetermined magnitude from being coupled to the operational circuit, comprising: bipolar transistor means having first and second current conducting electrodes coupled between a power supply voltage terminal and the input terminal, and a control electrode; first means coupled between the first current conducting electrode and the control electrode of the bipolar transistor means and selectively connecting the first current conducting electrode and the control electrode of the bipolar transistor means in response to an input signal coupled to the input terminal; and second means coupled between the input terminal and the control electrode of the bipolar transistor means and selectively connecting the control electrode and the second current electrode of the bipolar transistor means in response to the input signal are each an MOS transistor.
Claim 2
Dependent Claim 146 words
A semiconductor protection circuit coupled to an input terminal of an operational circuit for preventing positive and negative voltages exceeding a predetermined magnitude from being coupled to the operational circuit, comprising: bipolar transistor means having first and second current conducting electrodes coupled between a power supply voltage terminal and the input terminal, and a control electrode; first means coupled between the first current conducting electrode and the control electrode of the bipolar transistor means and selectively connecting the first current conducting electrode and the control electrode of the bipolar transistor means in response to an input signal coupled to the input terminal; and second means coupled between the input terminal and the control electrode of the bipolar transistor means and selectively connecting the control electrode and the second current electrode of the bipolar transistor means in response to the input signal are each an MOS transistor.
Claim 3
Dependent Claim 35 words
The semiconductor protection circuit of claim 1 wherein the first current conducting electrode of the bipolar transistor means is a collector and the second current conducting electrode of the bipolar transistor means is an emitter.
Claim 4
Dependent Claim 124 words
A semiconductor protection circuit for protecting an operational circuit from both positive and negative voltages having a magnitude greater than a predetermined voltages, comprising: a bipolar transistor having an emitter electrode coupled to an input terminal for receiving an input signal, a base electrode, and a collector electrode coupled to a power supply terminal; a first MOS transistor having a first current electrode coupled to the power supply terminal, a control electrode coupled to said input terminal, and a second current electrode coupled to the base electrode of the bipolar transistor; and a second MOS transistor having a first current electrode coupled to the base electrode of the coupled to said power supply terminal, and a second current electrode coupled to said input terminal.
Claim 5
Dependent Claim 124 words
A semiconductor protection circuit for protecting an operational circuit from both positive and negative voltages having a magnitude greater than a predetermined voltages, comprising: a bipolar transistor having an emitter electrode coupled to an input terminal for receiving an input signal, a base electrode, and a collector electrode coupled to a power supply terminal; a first MOS transistor having a first current electrode coupled to the power supply terminal, a control electrode coupled to said input terminal, and a second current electrode coupled to the base electrode of the bipolar transistor; and a second MOS transistor having a first current electrode coupled to the base electrode of the coupled to said power supply terminal, and a second current electrode coupled to said input terminal.
Claim 6
Dependent Claim 33 words
The semiconductor protection circuit of claim 3 wherein the power supply terminal is adapted to receive a positive power supply voltage, and the first and second MOS transistors are N-channel conductivity type transistors.
Claim 7
Dependent Claim 57 words
The semiconductor protection circuit of claim 3 wherein the first current electrode of the first MOS transistor is a drain, the second current electrode of the first MOS transistor is a source, the first current electrode of the second MOS transistor is a drain, and the second current electrode of the second MOS transistor is a source.
Claim 8
Dependent Claim 93 words
An input protection circuit comprising: an NPN bipolar transistor having an emitter coupled to an input terminal, a base, and a collector coupled to a power supply terminal; a first N-channel MOS transistor having a drain coupled to said power supply terminal, a gate coupled to said input terminal, and a source connected to the base of the bipolar transistor; and a second N-channel MOS transistor having a drain coupled to the base of the bipolar transistor, a gate coupled to said power supply terminal, and a source coupled to said input terminal.
Claim 9
Dependent Claim 93 words
An input protection circuit comprising: an NPN bipolar transistor having an emitter coupled to an input terminal, a base, and a collector coupled to a power supply terminal; a first N-channel MOS transistor having a drain coupled to said power supply terminal, a gate coupled to said input terminal, and a source connected to the base of the bipolar transistor; and a second N-channel MOS transistor having a drain coupled to the base of the bipolar transistor, a gate coupled to said power supply terminal, and a source coupled to said input terminal.
Claim 10
Dependent Claim 26 words
The input protection circuit of claim 6 wherein said power supply terminal is adapted to receive a positive supply voltage relative to a ground reference potential.

References Cited (Backward Citations)

US4302791A Cited
US4484244A Cited
US4704654A Cited
US4633283A Cited
US4698720A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-06-07 1991-12-07 1992-06-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-06-07 1995-12-07 1996-06-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-06-07 1999-12-07 2000-06-07 $7700.00 Window Closed / Lapsed

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