US4750026A
Expired / Lapsed
US
⏱️ 0.0 years remaining
C MOS IC and method of making the same
Assignee: Panasonic Holdings Corp
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Filing: 1985-11-19
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Granted: 1988-06-07
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Expires: 2005-11-19
Abstract
Abstract In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.
Inventors
- 👤 Shigeo Kuninobu
- 👤 Eisuke Ichinohe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/90; H10D84/903; H10D84/907; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
347 words
A complementary MOS I formed on a single semiconductor substrate comprising: a logic cell including a p-type MOS elements region and an n-type MOS elements regions which are faced to each other and disposed in a first direction, a plurality of said logic cells forming a logic circuit block and said p-type MOS elements regions of said logic cells being disposed proximate to each other and said n-type MOS elements regions of said logic cells being disposed prodximate to each other; a first metal wiring extending in said first direction for interconnection between said p-type MOS elements region and said n-type MOS elements region, thereby to make said logic cell operate as a desired logic gate or a feed-through wiring which passes through said logic circuit block; a second metal wiring extending in a second direction which is perpendicular to said first direction, along outer edges of said p-type MOS elements region and said n-type MOS elements region, and serving as wiring for power source potential and ground potential; said logic circuit block being formed in a manner that said logic cells are arranged in said second direction, and being disposed in said first direction; a third metal wiring extending in said second direction at a space between two neighboring logic circuit blocks; a polycrystalline silicon wiring disposed in said first direction crossing under said second metal wiring and insulated from said semiconductor substrate and from said second metal wiring, and led out in said first direction from said logic cell, said logic cells being coupled to each other by use of said polycrystalline silicon wiring and at least one of said first metal wiring and said third metal wiring; a diffused region disposed in said second direction along an inner edge of said each MOS elements region, said inner edge being neighboring with the other type MOS elements region in the same logic cell, for serving as electric wiring for power source potential or ground potential; and a fourth metal wiring disposed in said first direction for connecting said diffused region and said second metal wiring.
Claim 2
Dependent Claim
347 words
A complementary MOS I formed on a single semiconductor substrate comprising: a logic cell including a p-type MOS elements region and an n-type MOS elements regions which are faced to each other and disposed in a first direction, a plurality of said logic cells forming a logic circuit block and said p-type MOS elements regions of said logic cells being disposed proximate to each other and said n-type MOS elements regions of said logic cells being disposed prodximate to each other; a first metal wiring extending in said first direction for interconnection between said p-type MOS elements region and said n-type MOS elements region, thereby to make said logic cell operate as a desired logic gate or a feed-through wiring which passes through said logic circuit block; a second metal wiring extending in a second direction which is perpendicular to said first direction, along outer edges of said p-type MOS elements region and said n-type MOS elements region, and serving as wiring for power source potential and ground potential; said logic circuit block being formed in a manner that said logic cells are arranged in said second direction, and being disposed in said first direction; a third metal wiring extending in said second direction at a space between two neighboring logic circuit blocks; a polycrystalline silicon wiring disposed in said first direction crossing under said second metal wiring and insulated from said semiconductor substrate and from said second metal wiring, and led out in said first direction from said logic cell, said logic cells being coupled to each other by use of said polycrystalline silicon wiring and at least one of said first metal wiring and said third metal wiring; a diffused region disposed in said second direction along an inner edge of said each MOS elements region, said inner edge being neighboring with the other type MOS elements region in the same logic cell, for serving as electric wiring for power source potential or ground potential; and a fourth metal wiring disposed in said first direction for connecting said diffused region and said second metal wiring.
Claim 3
Dependent Claim
401 words
A complementary MOS IC formed on a single semiconductor substrate comprising: a logic cell including a p-type MOS elements region and an n-type MOS elements region which are faced to each other and disposed in a first direction, a plurality of said logic cells forming a logic circuit block and said p-type MOS elements regions of said logic cells being disposed proximate to each other and said n-type MOS elements regions of said logic cells being disposed proximate to each other; a first metal wiring extending in said first direction for interconnection between said p-type MOS elements region and said n-type MOS elements region, thereby to make said logic cell operate as a desired logic gate or a feed-through wiring which passes through said logic circuit block; a second metal wiring extending in a second direction which is perpendicular to said first direction, along outer edges of said p-type MOS elements region and said n-type MOS elements region, and serving as wiring for power source potential and ground potential; said logic circuit block being formed in a manner that said logic cells are arranged in said second direction, and being disposed in said first direction; a third metal wiring extending in said second direction at a space between two neighboring logic circuit blocks; a polycrystalline silicon wiring disposed in said first direction crossing under said second metal wiring and insulated from said semiconductor substrate and from said second metal wiring, and led out in said first direction from said logic cell; said logic cells being coupled to each other by use of said polycrystalline silicon wiring and at least one of said first metal wiring and said third metal wiring; a second polycrystalline silicon wiring having same kind of material as gate material and disposed on a field oxide between said p-type MOS elements region and said n-type MOS elements region, for connecting said logic cells belonging to said same logic circuit block, being led out in said second direction from said logic cell; a diffused region disposed in said second direction along an inner edge of said each MOS elements region, said inner edge being neighboring with the other type MOS elements region in the same logic cell, for serving as electric wiring for power source potential or ground potential, and a fourth metal wiring disposed in said first direction for connecting said diffused region and said second metal wiring.
Claim 4
Dependent Claim
401 words
A complementary MOS IC formed on a single semiconductor substrate comprising: a logic cell including a p-type MOS elements region and an n-type MOS elements region which are faced to each other and disposed in a first direction, a plurality of said logic cells forming a logic circuit block and said p-type MOS elements regions of said logic cells being disposed proximate to each other and said n-type MOS elements regions of said logic cells being disposed proximate to each other; a first metal wiring extending in said first direction for interconnection between said p-type MOS elements region and said n-type MOS elements region, thereby to make said logic cell operate as a desired logic gate or a feed-through wiring which passes through said logic circuit block; a second metal wiring extending in a second direction which is perpendicular to said first direction, along outer edges of said p-type MOS elements region and said n-type MOS elements region, and serving as wiring for power source potential and ground potential; said logic circuit block being formed in a manner that said logic cells are arranged in said second direction, and being disposed in said first direction; a third metal wiring extending in said second direction at a space between two neighboring logic circuit blocks; a polycrystalline silicon wiring disposed in said first direction crossing under said second metal wiring and insulated from said semiconductor substrate and from said second metal wiring, and led out in said first direction from said logic cell; said logic cells being coupled to each other by use of said polycrystalline silicon wiring and at least one of said first metal wiring and said third metal wiring; a second polycrystalline silicon wiring having same kind of material as gate material and disposed on a field oxide between said p-type MOS elements region and said n-type MOS elements region, for connecting said logic cells belonging to said same logic circuit block, being led out in said second direction from said logic cell; a diffused region disposed in said second direction along an inner edge of said each MOS elements region, said inner edge being neighboring with the other type MOS elements region in the same logic cell, for serving as electric wiring for power source potential or ground potential, and a fourth metal wiring disposed in said first direction for connecting said diffused region and said second metal wiring.
Claim 5
Dependent Claim
16 words
A complementary MOS IC in accordance with claim 2, wherein said metal wiring is aluminum wiring.
Claim 6
Dependent Claim
33 words
A complementary MOS IC in accordance with claim 2, wherein in neighboring two of said logic circuit blocks, MOS complementary element regions of the same conductivity types are disposed to neighbor each other.
Claim 7
Dependent Claim
21 words
A complementary MOS IC in accordance with claim 4, which further comprises guard bands encircling said regions of one conductivity type.
Claim 8
Dependent Claim
16 words
A complementary MOS IC in accordance with claim 1, wherein said metal wiring is aluminum wiring.
Claim 9
Dependent Claim
33 words
A complementary MOS IC in accordance with claim 1, wherein in neighboring two of said logic circuit blocks, MOS complementary element regions of the same conductivity types are disposed to neighbor each other.
Claim 10
Dependent Claim
21 words
A complementary MOS IC in accordance with claim 7, which further comprises guard bands encircling said regions of one conductivity type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |