Offset floating gate EPROM memory cell

Claim 1

An electronically programmable read only memory cell formed in a face of a semiconductor substrate of a first conductivity type, comprising: a pair of spaced apart thick oxide isolation regions defining an elongated channel of said substrate therebetween; a floating gate of conductive material having a predetermined length, overlying a portion of one of said isolation regions and a first portion of said elongated channel, and separated from said channel by a thin insulator layer, wherein at least approximately one half of said predetermined length of said floating gate overlies said portion of one of said isolation regions; a control layer of conductive material extending over said floating gate and over a portion of said channel not overlied by said floating gate, and separated from said floating gate and said channel by an insulator layer; and a buried diffusion region of a second conductivity type formed below said isolation regions; wherein the sides of said floating gate which define its width transverse to said channel are self-aligned with said control layer.