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US4749885A
Expired / Lapsed
US
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Nonsaturating bipolar logic gate having a low number of components and low power dissipation
Assignee: Unisys Corp
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Filing: 1987-02-17
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Granted: 1988-06-07
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Expires: 2007-02-17
Abstract
Abstract A two input nonsaturating bipolar logic gate consists of just two bipolar transistors plus a pair of resistors plus two voltage buses. One resistor has a resistance R C and it is connected from one of the voltage buses to the collector of both transistors. The second resistor has a resistance R E and it is connected from the other voltage bus to the emitter of both transistors. Those resistances R C and R E are selected such that R C /R E >1 and 0.1<(V CC -V BE )R C /R E <0.8 V BE where V BE is the base to emitter voltage at which each transistor turns on and V CC is the voltage between the two voltage buses.
Inventors
- 👤 Laszlo V. Gal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
169 words
An improved N input logic gate which consists of just N bipolar transistors having respective bases for receiving two level input signals, plus a pair of resistors, plus two voltage buses; a first resistor of said pair having a resistance R C and being connected from one of said voltage buses to the collector of all N transistors for generating output signals thereon; a second resistor of said pair having a resistance R E and being connected from the remaining voltage bus to the emitter of all N transistors; and wherein to reduce power dissipation in said gate and to generate said output signals with the same two levels as said input signals, the improvement comprises said resistance R C and R E being selected such that R C /R E >1 and 0.1<(V CC -V BE )R C /R E <0.8V BE where V BE is the base to emitter voltage at which each transistor turns on and V CC is the voltage between said two voltage buses.
Claim 2
Dependent Claim
169 words
An improved N input logic gate which consists of just N bipolar transistors having respective bases for receiving two level input signals, plus a pair of resistors, plus two voltage buses; a first resistor of said pair having a resistance R C and being connected from one of said voltage buses to the collector of all N transistors for generating output signals thereon; a second resistor of said pair having a resistance R E and being connected from the remaining voltage bus to the emitter of all N transistors; and wherein to reduce power dissipation in said gate and to generate said output signals with the same two levels as said input signals, the improvement comprises said resistance R C and R E being selected such that R C /R E >1 and 0.1<(V CC -V BE )R C /R E <0.8V BE where V BE is the base to emitter voltage at which each transistor turns on and V CC is the voltage between said two voltage buses.
Claim 3
Dependent Claim
13 words
A logic gate according to claim 1 wherein said transistors are NPN transistors.
Claim 4
Dependent Claim
13 words
A logic gate according to claim 1 wherein said transistors are PNP transistors.
Claim 5
Dependent Claim
13 words
A logic gate according to claim 1 wherein said transistors are silicon transistors.
Claim 6
Dependent Claim
13 words
A logic gate according to claim 1 wherein said transistors are germanium transistors.
Claim 7
Dependent Claim
14 words
A logic gate according to claim 1 wherein said transistors a gallium arsenide transistors.
Claim 8
Dependent Claim
18 words
A logic gate according to claim 1 wherein said voltage V CC is less than 2V BE .
Claim 9
Dependent Claim
141 words
An integrated circuit which includes a plurality of N input logic gates that are interconnected to each other without any level shifters between the gates; wherein each logic gate consists essentially of: N bipolar transistors, which are of a single conductivity type throughout said integrated circuit; said transistors having collectors that are connected through a first resistor of resistance R C to a first voltage bus; said transistors having emitters that are connected through a second resistor of resistance R E to a second voltage bus; and said resistance R C and R e being selected such that R C /R E >1 and 0.1<(V CC -V BE )R C /R E <0.8V BE where V BE is the base to emitter voltage at which each transistor turns on and V CC is the voltage between said first and second bus.
Claim 10
Dependent Claim
141 words
An integrated circuit which includes a plurality of N input logic gates that are interconnected to each other without any level shifters between the gates; wherein each logic gate consists essentially of: N bipolar transistors, which are of a single conductivity type throughout said integrated circuit; said transistors having collectors that are connected through a first resistor of resistance R C to a first voltage bus; said transistors having emitters that are connected through a second resistor of resistance R E to a second voltage bus; and said resistance R C and R e being selected such that R C /R E >1 and 0.1<(V CC -V BE )R C /R E <0.8V BE where V BE is the base to emitter voltage at which each transistor turns on and V CC is the voltage between said first and second bus.
Claim 11
Dependent Claim
15 words
An integrated circuit according to claim 8 wherein all of said transistors are NPN transistors.
Claim 12
Dependent Claim
18 words
An integrated circuit according to claim 8 wherein said voltage V CC is less than 2V BE .
References Cited (Backward Citations)
US3450896A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |