Circuit having an output referenced to a specific voltage in response to either an ECL or TTL input

Claim 2

A circuit comprising; an input terminal; an output terminal; a first supply voltage terminal; a second supply voltage terminal; a third supply voltage terminal; a fourth supply voltage terminal; first means coupled between said third and fourth supply voltage terminals and coupled to said output terminal for providing an output signal at said output terminal; and second means coupled between said first, second and fourth supply voltage terminals and coupled to said input terminal and said first means for biasing said first means in order to provide an output at said output terminal that is referenced to a second supply voltage when one of a first or a second condition occur, said first condition being when a first supply voltage is applied to said first and third supply voltage terminals and said second supply voltage is applied to said second and fourth supply voltage terminals and an input signal is referenced below said first supply voltage, said second condition being when said first supply voltage is applied to said first supply voltage terminal, said second supply voltage is applied to said second and third supply voltage terminals, and a third supply voltage is applied to said fourth supply voltage terminal and said input signal is referenced above said second supply voltage, said first, second and third supply voltages being successively smaller in value.

Claim 3

The circuit according to claim 1 wherein said second means comprises: third means coupled between said input terminal and a node for shifting the voltage level of said input signal; fourth means coupled between said first supply voltage terminal and said node for selectively applying said first supply voltage to said node; fifth means coupled between said node and said second supply voltage terminal for selectively sinking a current from said node; and sixth means coupled between said first, second and third supply voltage terminals and to said fourth means for biasing said fourth means.

Claim 4

The circuit according to claim 2 wherein said sixth means comprises: seventh means coupled between said second supply voltage terminal and both said first and third supply voltage terminal and to said fourth means for biasing said fourth means; and eighth means coupled between said seventh means and said second supply voltage terminal and to said third supply voltage terminal for selectively sinking current from said seventh means.

Claim 5

The circuit according to claim 2 wherein said fourth means comprises a first transistor having its collector-emitter path coupled between said first supply voltage terminal and said node.

Claim 6

The circuit according to claim 4 wherein said fifth means comprises a second transistor having its collector-emitter path coupled between said node and said fourth supply voltage terminal, and a base coupled to said second supply voltage terminal.

Claim 7

The circuit according to claim 4 wherein said fifth means comprises: a second transistor having its emitter coupled to said fourth supply voltage terminal and a base coupled to said second supply voltage terminal; and a third transistor having its collector-emitter path coupled between said node and a collector of said second transistor, and a base coupled to a voltage reference.

Claim 8

The circuit according to claim 6 wherein said first means comprises: a first resistor; a fourth transistor having a collector coupled to said third supply voltage terminal by said first resistor and to said output terminal; and a fifth transistor having its collector-emitter path coupled between an emitter of said fourth transistor and said fourth supply voltage terminal, and a base coupled to said base of said third transistor.

Claim 9

The circuit according to claim 7 wherein said sixth means comprises: a second resistor; a third resistor; a sixth transistor having its collector-emitter path coupled between said fourth means and said second supply voltage terminal and a base coupled by said second resistor to said third supply voltage terminal; a seventh transistor having its collector-emitter path coupled between said base of said sixth transistor and said second supply voltage terminal; an eighth transistor having its collector-emitter path coupled between said first supply voltage terminal and a base of said seventh transistor; a ninth transistor having its collector-emitter path coupled between said first supply voltage terminal and a base of said eighth transistor and a base coupled to said collector of said sixth transistor; and a tenth transistor having its collector-emitter path coupled between said bases of both said seventh and eighth transistors and said second supply voltage terminal, and a base coupled to said third supply voltage terminal by said third resistor.

Claim 10

A circuit comprising: a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for selectively receiving said first supply voltage or said second supply voltage; a fourth supply voltage terminal for selectively receiving said second supply voltage or a third supply voltage, said first, second and third supply voltages being successively smaller in value; an input terminal for receiving an input signal referenced either above said third supply voltage terminal or referenced below said third supply voltage terminal; an output terminal; first means coupled between said third and fourth supply voltage terminals and coupled to said output terminal for providing an output signal at said output terminal referenced below said second supply voltage; and second means coupled between said first, second and fourth supply voltage terminals and coupled to said input terminal and said first means for biasing said first means so that said first means provides said output when one of a first condition or a second condition occurs, said first condition occurring when said first and second supply voltages are applied to said third and fourth supply voltage terminals, respectively, and said input signal is referenced below said third supply voltage terminal, said second condition occurring when said second and third supply voltages are applied to said third and fourth supply voltage terminals, respectively, and said input signal is referenced above said third supply voltage terminal.

Claim 11

A circuit comprising: a first supply voltage terminal for receiving a first supply voltage; a second supply voltage terminal for receiving a second supply voltage; a third supply voltage terminal for selectively receiving said first supply voltage or said second supply voltage; a fourth supply voltage terminal for selectively receiving said second supply voltage or a third supply voltage, said first, second and third supply voltages being successively smaller in value; an input terminal for receiving an input signal referenced either above said third supply voltage terminal or referenced below said third supply voltage terminal; an output terminal; first means coupled between said third and fourth supply voltage terminals and coupled to said output terminal for providing an output signal at said output terminal referenced below said second supply voltage; and second means coupled between said first, second and fourth supply voltage terminals and coupled to said input terminal and said first means for biasing said first means so that said first means provides said output when one of a first condition or a second condition occurs, said first condition occurring when said first and second supply voltages are applied to said third and fourth supply voltage terminals, respectively, and said input signal is referenced below said third supply voltage terminal, said second condition occurring when said second and third supply voltages are applied to said third and fourth supply voltage terminals, respectively, and said input signal is referenced above said third supply voltage terminal.

Claim 12

The circuit according to claim 9 wherein said second means comprises: third means coupled between said input terminal and a node for shifting the voltage level of said input signal; fourth means coupled between said first supply voltage terminal and said node for selectively applying said first supply voltage to said node; fifth means coupled between said node and said second supply voltage terminal for selectively sinking a current from said node; and sixth means coupled between said first, second and third supply voltage terminals and to said fourth means for biasing said fourth means.

Claim 13

The circuit according to claim 10 wherein said sixth means comprises: seventh means coupled between said second supply voltage terminal and both said first and third supply voltage terminal and to said fourth means for biasing said fourth means; and eighth means coupled between said seventh means and said second supply voltage terminal and to said third supply voltage terminal for selectively sinking current from said seventh means.

Claim 14

The circuit according to claim 10 wherein said fourth means comprises a first transistor having its base emitter path coupled between said first supply voltage terminal and said node.

Claim 15

The circuit according to claim 12 wherein said fifth means comprises a second transistor having its collector-emitter path coupled between said node and said fourth supply voltage terminal, and a base coupled to said second supply voltage terminal.

Claim 16

The circuit according to claim 12 wherein said fifth means comprises: a second transistor having its emitter coupled to said fourth supply voltage terminal and a base coupled to said second supply voltage terminal; and a third transistor having its collector-emitter path coupled between said node and a collector of said second transistor, and a base coupled to a reference voltage.

Claim 17

The circuit according to claim 14 wherein said first means comprises: a first resistor; a fourth transistor having a collector coupled to said third supply voltage terminal by said first resistor and to said output terminal; and a fifth transistor having its collector-emitter path coupled between an emitter of said fourth transistor and said fourth supply voltage terminal, and a base coupled to said base of said third transistor.

Claim 18

The circuit according to claim 15 wherein said sixth means comprises: a second resistor; a third resistor; a sixth transistor having its collector-emitter path coupled between said fourth means and said second supply voltage terminal and a base coupled by said second resistor to said third supply voltage terminal; a seventh transistor having its collectoremitter path coupled between said base of said sixth transistor and said second supply voltage terminal; an eight transistor having its collector-emitter path coupled between said first supply voltage terminal and a base of said seventh transistor; a ninth transistor having its collector-emitter path coupled between said first supply voltage terminal and a base of said eighth transistor and a base coupled to said collector of said sixth transistor; and a tenth transistor having its collector-emitter path coupled between said bases of both said seventh and eighth transistors and said second supply voltage terminal, and a base coupled to said third supply voltage terminal by said third resistor.