Process of fabricating a semiconductor IC involving simultaneous sputter etching and deposition

Claim 1

A process of fabricating a semiconductor IC having a plurality of metal wiring conductor layers on a semiconductor substrate and an insulation layer between the metal wiring conductor layers, the insulation layer being formed of a silicon oxide film formed by RF bias-sputtering, said process comprising the steps of: (a) forming a silicon oxide film having a thickness equal to the sum of the thickness of the underlying metal wiring conductor layer and the ultimate interlayer insulation layer, by means of RF bias sputtering under such a condition that the deposition rate and the etching rate on a pattern surface 45° inclined with respect to the reference surface of the semiconductor substrate are substantially equal to each other, part of the silicon oxide film over the underlying metal wiring conductor layer being protruded, (b) forming a trench in part of the silicon oxide film covering the metal wiring conductor layer, the trench having a depth equal to the metal wiring conductor layer that is covered by the silicon oxide, and (c) etching the silicon oxide by RF bias sputtering under such a condition that the deposition rate and etching rate on a pattern surface parallel to the reference surface of the semiconductor substrate are substantially equal to each other, until the protrusion of the silicon oxide film over the metal wiring conductor is removed so that the entire silicon oxide film is planarized.