Start bit detecting circuit

Claim 1

In a receiving circuit for a digital signal of three-values bidirectional-current, start-stop synchronization having a zero-level at the non-existence of a signal and a (+) side level and a (-) side level at the existence of a signal, a start bit detecting circuit comprising: a waveform reshaper for converting a received waveform from a transmission line into a binary signal of a (+) side received signal and a (-) side received signal respectively by shaping it with two (+) side and (-) side threshold values for differentiating the non-existence of a signal and the (+) side received signal from the non-existence of a signal and the (-) side received signal; a detection and start circuit for monitoring the pulse width of the (+) side or (-) side received signal and generating a detection start signal upon detection of a pulse width greater than a predetermined value; a decision circuit whereby while the detection start signal is generated, the (+) side and (-) side received signals are monitored at a plurality of decision points, when the received signals differ from a predetermined pattern at two or more decision points, a detection stop pulse is applied to the detection start circuit to stop the detection start signal, and when the received signals coincide with the predetermined pattern at two or more decision points, a pattern information signal representing coincidence or noncoincidence at each decision point of the pattern are output together with a coincidence signal; a plurality of clock pulse generators which detect the rise of the (+) side or (-) side received signal at two or more decision points and generate clock pulses on the basis of each decision point; and a clock pulse selector for selecting one of the plurality of clock pulse generators in accordance with the coincidence signal and the pattern information.