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US3749840A Expired / Lapsed US ⏱️ 0.0 years remaining

Tdm telecommunication system designed for transmission of supervisory signals

Assignee: Italtel SpA
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Filing: 1972-01-03
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Granted: 1973-07-31
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Expires: 1992-01-03
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Abstract

Abstract To indicate the active or inactive condition of any one of a group of n telegraph lines transmitting in interleaved relationship over a common channel, each line is assigned a 5-bit time slot in a recurrent cycle of n+1 time slots, the extra slot being utilized at the beginning of each cycle to register the 4bit address of the first nontransmitting line in the series which is either idle (stop signal) or about to become active (start signal). In the time slot of the line so identified, a discriminating bit differentiating between ''''start'''' and ''''stop'''' conditions is accompanied by the four address bits identifying the next nontransmitting line in the series, and so forth; the extra time slot eliminates the need for a 6th bit to accommodate the start and stop signals in a 32-character telegraphy code.

Inventors

  • 👤 P Fornasiero
  • 👤 S Tomasi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 11:43
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/12; H04J3/24

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 687 words
A time-division-multiplex system for the transmission of 2m different characters of m bits each along with at least two supervisory signals from n incoming lines to n associated outgoing lines over a common channel extending between an input terminal and an output terminal, with n at most equal to 2m 1-1, comprising: storage means at said input terminal having a capacity of n+1 time slots of m bits each, including n message slots respectively assigned to said incoming lines and a service slot; read-out means connected to said storage means for periodically delivering the contents of said time slots in cyclic succession to said common channel for transmission to said output terminal; a set of n multiplexing registers each connected at said input terminal to one of said incoming lines for receiving therefrom a succession of characters to be transmitted over said common channel as part of a composite word; an ancillary register at said input terminal with a storage capacity of m bits including at least one discriminating bit differentiating between a plurality of line conditions and a multibit address code identifying any one of said incoming lines; first transfer means at said input terminal for periodically scanning said multiplexing registers to enter the characters stored therein, one character at a time, in the respectively assigned time slot of said storage means during a recurring operating cycle; second transfer means at said input terminal operable to enter the contents of said ancillary register in a time slot of said storage means not occupied by a character for inclusion in said composite word; a set of n monitoring circuits at said input terminal respectively connected to said lines for ascertaining the existence of any of said line conditions on an inactive line not engaged in character transmission; inscription means at said input terminal for inserting into said ancillary register a discriminating bit indicating a line condition detected by any one of said monitoring circuits together with the address code of the inactive line affected by said condition; switch means at said input terminal for successively connecting said monitoring circuits to said inscription means in a predetermined sequence during each operating cycle to load said ancillary register in the presence of a detected line condition on an inactive line; programming means at said input terminal controlling the operation of said first and second transfer means, said inscription means, said read-out means and said switch means, said second transfer means being controlled by said programming means to enter the address code of a first inactive line in said service slot, the address code of a second inactive line in the message slot of the same composite word assigned to said first inactive line, and so forth, with simultaneous entry of respective discriminating bits in all but one of the time slots receiving said address codes; a set of n demultiplexing registers for said characters respectively connectable to said outgoing lines at said output terminal; distributing means at said output terminal for selectively directing respective characters from said common channel to said demultiplexing registers for retransmission over said outgoing lines; a further register at said output terminal connected to said common channel for the temporary storage of any m-bit combination arriving thereover; decoding means connected to said further register for deriving respective identify signal from address codes stored therein; a set of n line-identification units respectively actuatable by said identity signals; synchronziing means at said output terminal responsive to said composite word for enabling said decoding means to actuate a first line-identification unit under the control of an address code in said service slot, to actuate a second lineidentification unit under the control of an address code in the message slot assigned to the line identified by said first unit, and so forth; signal-generating means at said output terminal connected to said further register for operation in accordance with a stored discriminating bit under the control of an actuated lineidentification unit; and selector means at said output terminal controlled by said lineidentification units for temporarily switching any outgoing line identified thereby from the associated demultiplexing register to said signal-generating means.
Claim 2
Dependent Claim 687 words
A time-division-multiplex system for the transmission of 2m different characters of m bits each along with at least two supervisory signals from n incoming lines to n associated outgoing lines over a common channel extending between an input terminal and an output terminal, with n at most equal to 2m 1-1, comprising: storage means at said input terminal having a capacity of n+1 time slots of m bits each, including n message slots respectively assigned to said incoming lines and a service slot; read-out means connected to said storage means for periodically delivering the contents of said time slots in cyclic succession to said common channel for transmission to said output terminal; a set of n multiplexing registers each connected at said input terminal to one of said incoming lines for receiving therefrom a succession of characters to be transmitted over said common channel as part of a composite word; an ancillary register at said input terminal with a storage capacity of m bits including at least one discriminating bit differentiating between a plurality of line conditions and a multibit address code identifying any one of said incoming lines; first transfer means at said input terminal for periodically scanning said multiplexing registers to enter the characters stored therein, one character at a time, in the respectively assigned time slot of said storage means during a recurring operating cycle; second transfer means at said input terminal operable to enter the contents of said ancillary register in a time slot of said storage means not occupied by a character for inclusion in said composite word; a set of n monitoring circuits at said input terminal respectively connected to said lines for ascertaining the existence of any of said line conditions on an inactive line not engaged in character transmission; inscription means at said input terminal for inserting into said ancillary register a discriminating bit indicating a line condition detected by any one of said monitoring circuits together with the address code of the inactive line affected by said condition; switch means at said input terminal for successively connecting said monitoring circuits to said inscription means in a predetermined sequence during each operating cycle to load said ancillary register in the presence of a detected line condition on an inactive line; programming means at said input terminal controlling the operation of said first and second transfer means, said inscription means, said read-out means and said switch means, said second transfer means being controlled by said programming means to enter the address code of a first inactive line in said service slot, the address code of a second inactive line in the message slot of the same composite word assigned to said first inactive line, and so forth, with simultaneous entry of respective discriminating bits in all but one of the time slots receiving said address codes; a set of n demultiplexing registers for said characters respectively connectable to said outgoing lines at said output terminal; distributing means at said output terminal for selectively directing respective characters from said common channel to said demultiplexing registers for retransmission over said outgoing lines; a further register at said output terminal connected to said common channel for the temporary storage of any m-bit combination arriving thereover; decoding means connected to said further register for deriving respective identify signal from address codes stored therein; a set of n line-identification units respectively actuatable by said identity signals; synchronziing means at said output terminal responsive to said composite word for enabling said decoding means to actuate a first line-identification unit under the control of an address code in said service slot, to actuate a second lineidentification unit under the control of an address code in the message slot assigned to the line identified by said first unit, and so forth; signal-generating means at said output terminal connected to said further register for operation in accordance with a stored discriminating bit under the control of an actuated lineidentification unit; and selector means at said output terminal controlled by said lineidentification units for temporarily switching any outgoing line identified thereby from the associated demultiplexing register to said signal-generating means.
Claim 3
Dependent Claim 42 words
A system as defined in claim 1 wherein said inscription means includes a timing circuit for establishing said predetermined sequence in the reverse order of the delivery of the contents of said time slots to said common channel by said transfer means.
Claim 4
Dependent Claim 81 words
A system as defined in claim 2 wherein said timing circuit includes blocking means for delaying the insertion of an address code into said ancillary register until after the entry of an accompanying discriminating bit together with a previously inserted address code in a time slot of said storage means whereBy each address code in a message slot is paired with a discriminating bit relating to the condition of the line identified by an address code in a preceding time slot.
Claim 5
Dependent Claim 15 words
A system as defined in claim 1 wherein said storage means comprises a circulating memory.
Claim 6
Dependent Claim 89 words
A system as defined in claim 1 wherein said discriminating bit has a first value signifying an idle line condition and a second value signifying incipient transmission over a line, said monitoring circuits comprising first voltage-detecting means connected across each incoming line upstream of the corresponding multiplexing register for the generation of a start signal in response to incipient line energization and second voltage-detecting means connected across each incoming line downstream of the corresponding multiplexing register for the generation of a stop signal upon the cessation of character transmission.
Claim 7
Dependent Claim 92 words
A system as defined in claim 5 wherein said programming means divides said operating cycle into a first period for the operation of said first transfer means, a second period for the operation of said switch means, said inscription means and said second transfer means, and a third period for the operation of said read-out means, said second voltage-detecting means comprising a set of n flip-flops connected to be set by said programming means in said third period and to be reset by voltage on the associated line in said first period.
Claim 8
Independent Claim 317 words
A method of multiplexing binary messages from n incoming lines for transmission over a common channel to n associated outgoing line, said message consisting of m-bit characters selected from 2m different code combinations, together with at least two supervisory signals relating to different line conditions, m being at most equal to 2m 1-1, comprising the steps of: assigning to each incoming line a message slot of m bits in a recurrent cycle of n+ 1 time slots, the extra time slot being used as a service slot accommodating an address code of less than m bits identifying any one of said incoming lines; entering a character from each active line in the assigned message slot for transmission in interleaved relationship over said common channel as part of a composite word; entering in said service slot, for transmission as part of said composite word, the address code of a first inactive line not engaged in character transmission; entering the address code of a second inactive line in the message slot of the same composite word assigned to said first inactive line, and so forth; entering at least one discriminating bit, signifying the condition of an inactive line, in each but one of the time slots receiving said acdress codes; detecting, at the remote end of said common channel, an address code appearing in the service slot of a received composite word and determining therefrom the identity of said first inactive line; detecting, at said remote end, an address code appearing in the message slot of the same composite word assigned to said first inactive line and determining therefrom the identity of said second inactive line, and so forth; extracting from said composite word, at said remote end, the discriminating bits relating to said inactive lines; and retransmitting line-condition signals derived from the extracted discriminating bits over respective outgoing lines associated with the lines identified from said address codes.
Claim 9
Independent Claim 317 words
A method of multiplexing binary messages from n incoming lines for transmission over a common channel to n associated outgoing line, said message consisting of m-bit characters selected from 2m different code combinations, together with at least two supervisory signals relating to different line conditions, m being at most equal to 2m 1-1, comprising the steps of: assigning to each incoming line a message slot of m bits in a recurrent cycle of n+ 1 time slots, the extra time slot being used as a service slot accommodating an address code of less than m bits identifying any one of said incoming lines; entering a character from each active line in the assigned message slot for transmission in interleaved relationship over said common channel as part of a composite word; entering in said service slot, for transmission as part of said composite word, the address code of a first inactive line not engaged in character transmission; entering the address code of a second inactive line in the message slot of the same composite word assigned to said first inactive line, and so forth; entering at least one discriminating bit, signifying the condition of an inactive line, in each but one of the time slots receiving said acdress codes; detecting, at the remote end of said common channel, an address code appearing in the service slot of a received composite word and determining therefrom the identity of said first inactive line; detecting, at said remote end, an address code appearing in the message slot of the same composite word assigned to said first inactive line and determining therefrom the identity of said second inactive line, and so forth; extracting from said composite word, at said remote end, the discriminating bits relating to said inactive lines; and retransmitting line-condition signals derived from the extracted discriminating bits over respective outgoing lines associated with the lines identified from said address codes.
Claim 10
Dependent Claim 25 words
A method as defined in claim 7 wherein said discriminating bits are entered only in message slots, said service slot containing only an address code.
Claim 11
Dependent Claim 30 words
A method as defined in claim 7 wherein said discriminating bit has a first value signifying an idle line condition and a second value signifying incipient transmission over a line.
Claim 12
Dependent Claim 21 words
A method as defined in claim 9 wherein each character consists of 5 bits, each address code consisting of 4 bits.

References Cited (Backward Citations)

US3560662A Cited
US3686442A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-07-30 1977-01-29 1977-07-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-07-30 1981-01-29 1981-07-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-07-30 1985-01-29 1985-07-31 $7700.00 Window Closed / Lapsed

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